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參數(shù)資料
| 型號(hào)： | DM74LS164N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Quad Buffer with 3-STATE Outputs |
| 中文描述： | LS SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-14 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 61K |
| 代理商： | DM74LS164N |
2000 Fairchild Semiconductor Corporation
DS006398
www.fairchildsemi.com
August 1986
Revised April 2000
D
DM74LS164
8-Bit Serial In/Parallel Out Shift Register
General Description
These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input
inhibits entry of the new data, and resets the first flip-flop to
the low level at the next clock pulse, thus providing com-
plete control over incoming data. A high logic level on
either input enables the other input, which will then deter-
mine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is HIGH or LOW, but only
information meeting the setup and hold time requirements
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.
Features
I
Gated (enable/disable) serial inputs
I
Fully buffered clock and serial inputs
I
Asynchronous clear
I
Typical clock frequency 36 MHz
I
Typical power dissipation 80 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don't Care (any input, including transitions)
↑
=
Transition from LOW-to-HIGH level
Q
A0
, Q
B0
, Q
H0
=
The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established.
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
before the most recent
↑
transition of the
clock; indicates a one-bit shift.
Order Number
DM74LS164M
DM74LS164N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Clock
X
L
↑
↑
↑
Outputs
Q
B
L
Q
B0
Q
An
Q
An
Q
An
Clear
L
H
H
H
H
A
X
X
H
L
X
B
X
X
H
X
L
Q
A
L
Q
A0
H
L
L
...
...
...
...
...
...
Q
H
L
Q
H0
Q
Gn
Q
Gn
Q
Gn
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| DM74LS166M | Quad Buffer with 3-STATE Outputs; Package: TSSOP; No of Pins: 14; Container: Rail |
| DM74LS166N | Quad Buffer with 3-STATE Outputs; Package: TSSOP; No of Pins: 14; Container: Tape & Reel |
| DM74LS166WM | Quad Buffer with 3-STATE Outputs |
| DM74LS166 | 8-Bit Parallel-In/Serial-Out Shift Register(8位并行輸入/串行輸出的移位寄存器) |
| DM74LS169 | Quad Buffer with 3-STATE Outputs; Package: SOIC; No of Pins: 14; Container: Rail |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM74LS165 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74LS165M | 功能描述:計(jì)數(shù)器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS165MX | 功能描述:計(jì)數(shù)器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS165N | 功能描述:計(jì)數(shù)器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS165WM | 功能描述:計(jì)數(shù)器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類(lèi)型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類(lèi)型: 輸入線路數(shù)量:1 輸出類(lèi)型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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