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參數(shù)資料
| 型號： | DM512K36ST6-15I |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 120K |
| 代理商： | DM512K36ST6-15I |
Enhanced
Memory Systems Inc.
DM512K32ST6/DM512K36ST6 Mutibank EDO
512Kbx 32/512Kbx 36 EDRAMSIMM
ProductSpecifcaton
1996 Enhanced Memory Sytems Inc
, 1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM
Fax
(719) 488-9095; http://wwwcsn.net/ramtron/enhanced 38-2117-000
80921
The information contained herein is subject to change wthout notice. Enhanced reserves the
right to change or discontinue this product wthout notice.
Features
I
4KByte SRAMCache Memory for 12ns RandomReads Wthin Four
Actives Pages (Multibank Cache)
I
Fast DRAMArray for 30ns Access to Any NewPage
I
Write Posting Register for 12ns RandomWrites and Burst Writes
Wthin a Page (Hit or Mss)
I
1KByte Wde DRAMto SRAMBus for 56.8 Ggabytes/Sec Cache Fill
I
On-chip Cache Hit/Mss Comparators Maintain Cache Coherency
on Writes
I
EDOMode for 83 MHz Non-Interleave Burst Rate
I
Hidden Precharge and Refresh Cycles
I
Extended 64ms Refresh Period for LowStandby Power
I
Standard CMOS/TTL Compatible I/OLevels and +5 Volt Supply
I
Compatibility wth JEDEC 512K x 32/36 DRAMSIMMConfiguration
Allows Performance Upgrade in System
I
Industrial Temperature Range Option
Description
The Enhanced Memory Systems 2MB EDRAMSIMMmodule
provides a single memory module solution for the main memory or
local memory of fast embedded control, DSP and other high
performance systems. Due to its fast 12ns cache rowregister, the
EDRAMmemory module supports zero-wait-state burst read
operations at up to 83MHz bus rates in a non-interleave configuration
and >100MHz bus rates wth a two-way interleave configuration.
On-chip write posting and fast page mode operation supports
12ns write and burst write operations. On a cache mss, the fast
DRAMarray reloads the entire 1KByte cache over a 1KByte-wde bus
in 18ns for an effective bandwdth of 56.8 Gbytes/sec. This means
very lowlatency and fewer wait states on a cache mss than a non-
integrated cache/DRAMsolution. The JEDEC compatible 72-bit SIMM
configuration allows a single memory controller to be designed to
support either JEDEC slowDRAMs or high speed EDRAMs to provide
a simple upgrade path to higher systemperformance.
Architecture
The DM512K36ST6
achieves 512K x 36 density by
mounting five 512K x 8
EDRAMs, packaged in 44-pin
plastic TSOP-IIpackages, on a
multi-layer substrate. Four
2203 devices and one
DM2213 device provide data
and parity storage. The
DM512K32 contains four
2203 devices for data only
The EDRAMmemory
module architectureis very
simlar to a standard 2MB
DRAMmodule wth the
addition of an integrated
cache and on-chip control which allows it to operate much like a
page mode or static column DRAM
The EDRAMs SRAMcache is integrated into the DRAMarray as
tightly coupled rowregisters. The 512K x 32/36 EDRAMSIMMhas a
total of four independent DRAMmemory banks each wth its own 256
x 32/36 SRAMrowregister. Memory reads always occur fromthe
cache rowregister of one of these banks as specified by rowaddress
bits A
8
and A
9
(bank select). When the internal comparator detects
that the rowaddress matches the last rowread fromany of the four
DRAMbanks (page hit), the SRAMis accessed and data is available
on the output pins in 12ns fromcolumn address input. Subsequent
reads wthin the page (burst reads or randomreads) can continue at
12ns cycle time. When the rowaddress does not match the last row
read fromany of the four DRAMbanks (page mss), the newDRAM
rowis accessed and loaded into the appropriate SRAMrowregister
and data is available on the output pins
all wthin 30ns fromrowenable.
Subsequent reads wthin the page (burst
reads or randomreads) can continue at
12ns cycle time. During either read hit or
read mss operations, the EDOoption
extends data output time to allowuse of
the full 83Mbyte/second bandwdth.
Since reads occur fromthe SRAM
cache, the DRAMprecharge can occur
during burst reads. This elimnates the
precharge time delay suffered by other
DRAMs and SDRAMs when accessing a
newpage. The EDRAMhas an
independent on-chip refresh counter and
dedicated refresh control pin to allowthe
DRAMarray to be refreshed concurrently
wth cache read operations (hidden
refresh).
/CAL
A
0
- A
10
W/R
/F
/RE
V
V
Sense Amps
& Column Write Select
Column Decoder
ARow
Latch
CC
SS
A
0
- A
9
4 - 256 X 36 Cache Pages
(Row Registers)
Array
2Mbyte + Parity
A
0
0-3, P
0, 2
- A
7
/G
/S
/WE
DQ
0-35
Column
ALatch
4 - 9 Bit
Comparators
I/O
Cand
LData
Refresh
Counter
R
Row Adress
Rand
Control
4 - Last Row
Latches
C
1-5
Functional Dagram
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DM512K64DT6-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) Module |
| DM512K64DT6-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) Module |
| DM512K64DTE-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) Module |
| DM512K64DTE-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) Module |
| DM512K72DT6-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) Module |
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