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參數(shù)資料
| 型號： | DM4M32SJ6-15L |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DM4M32SJ6-15L |
1-126
/RE
0, 2
/F
t
RE
t
MSU
t
MH
Don’t Care or Indeterminate
NOTES: 1.
2.
During /F refresh cycles, the status of W/R, /WE, A
0-10
, /CAL, /S, and /Gis a dont care.
/RE inactive cache reads may be performed in parallel wth /F refresh cycles.
t
RP
t
C
W/R, /F
t
RE
t
RP
t
ASR
t
RAH
Row
t
NRS
t
NRH
t
SSR
t
SHR
t
MSU
t
MH
/RE
0, 2
A
0-10
0-3
/CAL , /WE, /G
/S
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A
0
,
A
2-10
must be refreshed every 64ms interval. A
1
does not have to be cycled, but must remain valid
during rowaddress setup and hold times.
2. /RE refresh is write cycle wth no /CAL active cycle.
/F Refresh Cycle
/RE-Only Refresh
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