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參數(shù)資料
| 型號： | DM4M32SJ-15 |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DM4M32SJ-15 |
1-115
R = 828
5ns
V
GND
5.0V
Output
C = 50pf
R = 295
Load Circuit
Input Waveforms
≤
5ns
≤
IL
V
IL
V
IH
V
IH
Ambient Operating Temperature (T )
Description
Ratings
Output Voltage (V )
Power Supply Voltage (V )
Storage Temperature (T )
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Short Circuit O/P Current (I )
- 1 ~ 7v
- 1 ~ 7v
Input Voltage (V )
- 1 ~ 7v
0 ~ 70°C
-55 ~ 150°C
Class 1
50mA*
Description
Max
Pins
Input Capacitance
Input Capacitance
39pf
29pf
A
0-10
0-3
DQ
0-31
/G, /CAL
Input/Output Capacitance
18pf
/RE , /RE , W/R, /WE, /F, /S
Input Capacitance
19pf
Symbol
Parameters
Min
Max
Test Conditions
V
CC
V
IH
Supply Voltage
4.75V
5.25V
All Voltages Referenced to V
SS
V
I
I
V
IL
i(L)
O(L)
OH
V
OL
OV V 6.5V, All Other Pins Not Under Test = 0V
OV V , OV V 5.5V
I = - 5mA
I = 4.2mA
6.5V
0.8V
40μA
0.4V
20μA
2.4V
-1.0V
40μA
20μA
2.4V
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Level
Output Low Level
Symbol
Operating Current
-15 Max
Test Condition
I
CC1
Random Read
/RE, /CAL, /G and Addresses Cycling: t = t Minimum
All Control Inputs Stable V - 0.2V, Outputs Driven
/S, /F, W/R, /WE and A at V - 0.2V,
/RE and /CAL at V + 0.2V, I/O Option
See “Estimating EDRAM Operating Power” Application Note
/RE, /CAL, /WE and Addresses Cycling: t = t Minimum
/CAL, /WE and Addresses Cycling: t = t Minimum
4960mA
3840mA
36mA
4640mA
Fast Page Mode Read
Static Column Read
Standby
Random Write
Fast Page Mode Write
7520mA
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
6400mA
33MHz Typ
2400mA
2080mA
36mA
1920mA
3840mA
4640mA
Notes
2, 3
2, 4
2, 4
2, 3
2, 4
/CAL, /G and Addresses Cycling: t = t Minimum
/G and Addresses Cycling: t = t Minimum
(1) “33MHz Typ” refers to worst case I
expected in a systemoperating wth a 33MHz memory bus. In this typical example, page mode and randomreads refers to page burst hits and
msses. Writes are two clock cycle randomand page mode writes. See power applications note for further details. This parameter is not 100% tested or guaranteed.
(2) I
CC
is dependent on cycle rates and is measured wth CMOS levels and the outputs open.
(3) I
CC
is measured wth a maximumof one address change while /RE = V
IL
.
(4) I
CC
is measured wth a maximumof one address change while /CAL = V
IH
.
-12 Max
7520mA
4960mA
3840mA
36mA
6.4mA
Self-Refresh (-L Option)
6.4mA
6.4mA
1280mA
1280mA
6400mA
4640mA
Average Typical
Operating Current
I
CCT
1280mA
1
(1)
AC Test Load and Waveforms
Electrical Characteristics
Absolute MaximumRatings
(Beyond Which Permanent Damage Could Result)
Capacitance
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