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| 型號： | DM2223TME-15 |
| 英文描述： | Enhanced DRAM (EDRAM) |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存） |
| 文件頁數(shù)： | 1/30頁 |
| 文件大小： | 186K |
| 代理商： | DM2223TME-15 |
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DM2223/2233 Mutibank Burst EDO
EDRAM
512Kbx 8 EnhancedDynamc RAM
ProductSpecifcaton
1996 Enhanced Memory Systems Inc.,
1850 Ramtron Drive, Colorado Springs, CO
Telephone (719) 481-7000, Fax (719) 488-9095
80921
38-2106-001
The information contained herein is subject to change wthout notice.
Enhanced reserves the right to change or discontinue this product wthout notice.
Features
I
8Kbit SRAMCache Memory for 12ns RandomReads Wthin Four
Active Pages (Multibank Cache)
I
Fast 4Mbit DRAMArray for 30ns Access to Any NewPage
I
Write Posting Register for 12ns Randomor Burst Writes Wthin
a Page
I
5ns Output Enable Access Time Allows Fast Interleaving
I
Linear or Interleaved Burst Mode Configurable Wthout Mode
Register Load Cycles
I
Fast Page to Page Move or Read-Modify-Write Cycles
Description
The Enhanced Memory Systems 4Mb EDRAMcombines rawspeed
wth innovative architecture to offer the optimumcost-performance
solution for high performance local or main memory in computer and
embedded control systems. In most high speed applications, zero-wait-
state operation can be achieved wthout secondary SRAMcache for
systemclock speeds of up to 100MHz wthout interleaving or 132MHz
wth two-way interleaving. The EDRAMoutperforms conventional SRAM
cache plus DRAMor synchronous DRAMmemory systems by
mnimzing wait states on initial reads (hit or mss) and by elimnating
writeback delays. Architectural simlarity wth JEDEC DRAMs allows a
single memory controller design to support either slowJEDEC DRAMs
or high speed EDRAMs. A systemdesigned in this manner can provide
a simple upgrade path to higher systemperformance.
The 512K x 8 EDRAMhas a control and address interface
compatible wth the Enhanced 4Mx 1 and 1Mx 4 EDRAMproducts
so that EDRAMs of different organizations can be supported wth the
same controller design. The 512K x 8 EDRAMimplements the
followng additional features which can be supported on newdesigns:
I
On-chip Cache Hit/Mss Comparators Automatically Maintain Cache
Coherency Wthout External Cache Control
I
Output Latch Enable Allows Extended Data Output (EDO) for
Faster SystemOperation
I
Hidden Precharge and Refresh Cycles
I
Write-per-bit Option (DM2233) for Parity and Video Applications
I
Extended 64ms Refresh Period for LowStandby Power
I
LowProfile 300-Ml 44-Pin TSOP-II Package
I
Industrial Temperature Range Option
I
An optional synchronous burst mode for 100MHz burst transfers
or 132MHz two-way interleaved burst transfers.
I
A controllable output latch provides an extended data (EDO)
mode.
I
Cache size is increased from2Kbits to 8Kbits. The 8Kbit cache is
organized as four 256 x 8 direct mapped rowregisters. All row
registers can be accessed wthout clocking /RE.
I
Concurrent randompage write and cache reads fromfour cache
pages allows fast page-to-page move or read-modify-write cycles.
Archtecture
The EDRAMarchitectureincludes an integrated SRAMcache
which operates much like a page mode or static column DRAM
The EDRAMs SRAMcache is integrated into the DRAMarray as
tightly coupled rowregisters. The 512K x 8 EDRAMhas a total of four
independent DRAMmemory banks each wth its own 256 x 8 SRAM
rowregister. Memory reads always occur fromthe cache rowregister
of one of these banks as specified by column address bits A
8
and A
9
/CAL
BE
BM
0-2
A
0
-A
10
W/R
/F
/RE
V
CC
V
SS
Sense Amps
& Column Write Select
Column Decoder
Row
Address
Latch
4 - 256 X 8 Cache Pages
(Row Registers)
Memory
Array
(2048 X 256 X 8)
A
0
-A
9
A
0
-A
9
/G
/S
/WE
DQ
0
-DQ
7
Column
Address
Latch
and Burst
Control
4 - 9 Bit
Comparators
I/O
Control
and
Data
Latches
Refresh
Counter
R
Row Adress
and
Refresh
Control
4 - Last Row
Read Address
Latches
QLE
Functional Dagram
1
2
3
4
5
6
7
9
10
11
12
13
42
41
40
39
38
37
36
34
33
32
31
30
29
28
27
26
25
24
23
14
15
16
17
18
19
20
21
22
V
CC
/F
V
SS
DQ
0
V
CC
DQ
1
DQ
2
8
35
43
44
V
CC
DQ
7
V
CC
V
SS
DQ
3
QLE
V
CC
/G
DQ
4
V
SS
DQ
5
DQ
6
V
SS
BM
0
BM
1
V
SS
W/R
V
SS
V
SS
/RE
/CAL
V
CC
A
3
A
2
A
1
A
0
/WE
BE
BM
2
/S
A
10
A
9
A
8
A
7
A
6
A
5
A
4
Pin Configuration
Enhanced
Memory Systems Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM2223TME-20 | Enhanced DRAM (EDRAM) |
| DM2233T-12 | Enhanced DRAM (EDRAM) |
| DM2233T-12I | Enhanced DRAM (EDRAM) |
| DM2233T-15 | Enhanced DRAM (EDRAM) |
| DM2233T-15I | Enhanced DRAM (EDRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM2223TME-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2233T-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2233T-12I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2233T-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2233T-15I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
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