參數(shù)資料
型號(hào)： DM2212J1-15
英文描述： Enhanced DRAM (EDRAM)
中文描述： 增強(qiáng)的DRAM（eDRAM內(nèi)存）
文件頁(yè)數(shù)： 7/19頁(yè)
文件大?。?/td> 159K
代理商： DM2212J1-15
1-25
Symbol
Description
t
RGX
t
RQX1
(2,6)
t
RP
(7)
t
RP1
t
RRH
t
RSH
t
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
Row Precharge Time
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
Read Hold Time From Row Enable (Write Only)
Last Write Address Latch to End of Write
Row Enable to Column Address Latch Low For Second Write
9
20
8
0
ns
ns
ns
ns
ns
ns
Min
Max
Units
35
t
RP2
Row Precharge Time, Self-Refresh Mode
100
ns
Min
Max
Row Enable High to Output Turn-On After Write Miss
0
ns
-12
-15
12
RSW
t
RWL
t
SC
Last Write Enable to End of Write
ns
12
Column Address Cycle Time
ns
12
t
SHR
t
SQV
(1)
t
SQX
(2,3)
t
SQZ
(4,5)
Select Hold From Row Enable
ns
0
Chip Select Access Time
ns
12
Output Turn-On From Select Low
ns
12
0
Output Turn-Off From Chip Select
ns
8
0
t
SSR
Select Setup Time to Row Enable
ns
5
t
T
Transition Time (Rise and Fall)
ns
10
1
t
WC
Write Enable Cycle Time
ns
12
t
WCH
t
WHR
(7)
Column Address Latch Low to Write Enable Inactive Time
ns
5
t
WI
Write Enable Inactive Time
ns
5
(1) V
OUT
Timng Reference Point at 1.5V
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to V
OH
or V
OL
(3) MnimumSpecification is Referenced fromV
IH
and MaximumSpecification is Referenced fromV
IL
on Input Control Signal
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to V
OH
or V
OL
(5) MnimumSpecification is Referenced fromV
IL
and MaximumSpecification is Referenced fromV
IH
on Input Control Signal
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to t
RAC2
(7) For Write-Per-Bit Devices, t
WHR
is Limted By Data Input Setup Time, t
DS
t
WP
t
WQV
(1)
t
WRP
t
WRR
Write Enable Active Time
Write Enable Setup Time to Row Enable
Write to Read Recovery (Following Write Miss)
16
ns
ns
ns
5
Data Turn-Off From Write Enable Low
ns
t
WQX
(2,5)
t
WQZ
(3,4)
Data Output Turn-On From Write Enable High
ns
0
Data Valid From Write Enable High
ns
12
5
12
0
12
t
RE1
t
REF
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
Refresh Period
ms
64
8
ns
Write Enable Hold After /RE
ns
0
12
10
25
10
0
40
100
0
15
15
15
0
15
15
0
10
0
5
10
1
15
5
5
18
5
0
15
5
15
0
15
64
10
0
15
Switching Characteristics (continued)
V
CC
= 5V ± 5% (+5 Volt Option), V
CC
= 3.3V ± 0.3V% (+3.3 Volt Option), C
L
= 50pf, T
A
= 0 to 70°C (Commercial), -40 to 85°C (Industrial)
相關(guān)PDF資料
PDF描述
DM2212J1-15I Enhanced DRAM (EDRAM)
DM2212J1-15L Enhanced DRAM (EDRAM)
DM2200J1-12 Enhanced DRAM (EDRAM)
DM2200J1-12I Enhanced DRAM (EDRAM)
DM2200J1-12L Enhanced DRAM (EDRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM2212J1-15I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM)
DM2212J1-15L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM)
DM2212J-12 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM)
DM2212J-12I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM)
DM2212J-12L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM)
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