- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376760 > DM2203T-15 Enhanced DRAM (EDRAM) PDF資料下載
參數(shù)資料
| 型號： | DM2203T-15 |
| 英文描述： | Enhanced DRAM (EDRAM) |
| 中文描述： | 增強(qiáng)的DRAM（eDRAM內(nèi)存） |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 124K |
| 代理商： | DM2203T-15 |
2-39
/RE Ony RefreshOperation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAMrefresh, an /RE only refresh may
be performed using an externally supplied rowaddress. /RE
refresh is performed by executing a
write cycle
(W/R, /G and /F
are high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
operation. All combinations of addresses A
0-9
must be sequenced
every 64ms refresh period. A
10
does not need to be cycled. Read
refresh cycles are not allowed because a DRAMrefresh cycle does
not occur when a read refresh address matches the LRR address
latch.
Low Power Mode
The EDRAMenters its lowpower mode when /S is high. In this
mode, the internal DRAMcircuitry is powered down to reduce
standby current to 1mA.
IntializationCycles
A mnimumof eight /RE active initialization cycles (read,
write, or refresh) are required before normal operation is
guaranteed. Followng these start-up cycles, two read cycles to
different rowaddresses must be performed for each of the four
internal banks of DRAMto initialize the internal cache logic. Row
address bits A
8
and A
9
define the four internal DRAMbanks.
UnallowedMode
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
high.
ReducedPinCount Operation
Although it is desirable to use all EDRAMcontrol pins to
optimze systemperformance, the interface to the EDRAMmay be
simplified to reduce the number of control lines by either tying pins
to ground or by tying one or more control inputs together. The /S
input can be tied to ground if the lowpower standby mode is not
required. The QLE input can be tied lowif output latching is not
required, or it can be tied high if “extended data out” (hyper page
mode) is required. The /HIT output pin is not necessary for device
operation. The /CAL and /F pins can be tied together if hidden refresh
operation is not required. In this case, a CBR refresh (/CAL before
/RE) can be performed by holding the combined input lowprior to
/RE. A CBR refresh does not require that a rowaddress be supplied
when /RE is asserted. The timng is identical to /F refresh cycle
timng. The /WE input can be tied to /CAL if independent posting of
column addresses and data are not required during write operations.
In this case, both column address and write data wll be latched by
the combined input during writes. The W/R and /Ginputs can be tied
together if reads are not required during a write hit cycle. If these
techniques are used, the EDRAMwll require only three control lines
for operation (/RE, /CAS [combined /CAL, /F and /WE], and W/R
[combined W/R and /G]). The simplified control interface still allows
the fast page read/write cycle times, fast randomread/
write times,
and hidden precharge functions available wth the EDRAM
PinDescriptions
/RE — Row Enabe
This input is used to initiate DRAMread and write operations
and latch a rowaddress. It is not necessary to clock /RE to read
data fromthe most currently read SRAMrowregister. On read
operations, /RE can be brought high as soon as data is loaded into
cache to allowearly precharge.
/CAL — ColumnAddress Latch
This input is used to latch the column address and in
combination wth /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL
transitions low it latches the address present while /CAL was high.
/CAL can be toggled when /RE is lowor high. However, /CAL must
be high during the high-to-lowtransition of /RE except for /F
refresh cycles. If QLE is high during a read, /CAL wll hold data
output until it transitions low
W/R — Write/Read
This input along wth /F specifies the type of DRAMoperation
initiated on the lowgoing edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/F — Refresh
This input wll initiate a DRAMrefresh operation using the
internal refresh counter as an address source when /F is lowon the
lowgoing edge of /RE.
/WE — Write Enabe
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are
low
/G— Output Enabe
This input controls the gating of read data to the output data
pins during read operations.
/S — ChpSelect
This input is used to power up the I/Oand clock circuitry
When /S is high, the EDRAMremains in its lowpower mode. /S
must remain active throughout any read or write operation. Wth the
exception of /F refresh cycles, /RE should never be clocked when /S
is inactive.
DQ
0-7
— Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM On the DM2213 write-per-bit memory these pins
are also used to specify the bit mask used during write operations.
A
0-10
— Mutipex Address
These inputs are used to specify the rowand column
addresses of the EDRAMdata. The 11-bit rowaddress is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data fromthe SRAMcache or to
specify the write column address during write cycles.
QLE — Output LatchEnabe
This input enables the output latch. When QLE is low the
output latch is transparent. Data is latched when both /CAL and
QLE are high. This allows output data to be extended during either
static column or page mode read cycles.
/HT — Ht Pin
This output pin wll be driven during /RE active read or write
cycles to indicate the hit/mss status of the cycle.
V
CC
Power Suppy
These inputs are connected to the +5 volt power supply
V
SS
Ground
These inputs are connected to the power supply ground
connection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM2242J2-10 | Enhanced DRAM (EDRAM) |
| DM2252J2-10 | Enhanced DRAM (EDRAM) |
| DM2M32SJ-10 | Enhanced DRAM (EDRAM) Module |
| DM2M36SJ6-10 | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-10 | Enhanced DRAM (EDRAM) Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM2203T-15I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2203T-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2203TME-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2203TME-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2212J-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。