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參數(shù)資料
| 型號： | DM2202T1-15I |
| 英文描述： | Enhanced DRAM (EDRAM) |
| 中文描述： | 增強(qiáng)的DRAM（eDRAM內(nèi)存） |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 159K |
| 代理商： | DM2202T1-15I |
1-21
read-modify-write, write-verify or randomread-write sequences
wthin the page wth 12ns cycle times (the first read cannot
complete until after time t
RAC2
). At the end of a write sequence
(after /CAL and /WE are brought high and t
RE
is satisfied), /RE can
be brought high to precharge the memory It is possible to perform
cache reads concurrently wth precharge. During write sequences,
a write operation is not performed unless both /CAL and /WE are
low As a result, the /CAL input can be used as a byte write select in
multi-chip systems. If /CAL is not clocked on a write sequence, the
memory wll performa /RE only refresh to the selected rowand
data wll remain unmodified.
DRAMWrite Mss
If a DRAMwrite request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high, the EDRAMwll compare the newrow
address to the LRR address latch (an 11-bit latch loaded on each
/RE active read mss cycle). If the rowaddress does not match, the
EDRAMwll write data to the DRAMarray only and contents of the
current cache are not modified. The write address and data are
posted to the DRAMas soon as the column address is latched by
bringing /CAL lowand the write data is latched by bringing /WE
low The write address and data can be latched very quickly after
the fall of /RE (t
RAH
+ t
ASC
for the column address and t
DS
for the
data). During a write burst sequence, the second write data can be
posted at time t
RSW
after /RE. Subsequent writes wthin a page can
occur wth write cycle time t
PC
. During a write mss sequence,
cache reads are inhibited and the output buffers are disabled
(independently of /G) until time t
WRR
after /RE goes high. At the
end of a write sequence (after /CAL and /WE are brought high and
t
RE
is satisfied), /RE can be brought high to precharge the memory
It is possible to performcache reads concurrently wth the
precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low As a result, /CAL can
be used as a byte write select in multi-chip systems. If /CAL is not
clocked on a write sequence, the memory wll performa /RE only
refresh to the selected rowand data wll remain unmodified.
/RE Inactive Operation
It is possible to read data fromthe SRAMcache wthout clocking
/RE. This option is desirable when the external control logic is
capable of fast hit/mss comparison. In this case, the controller can
avoid the time required to performrow/column multiplexing on hit
cycles. This capability also allows the EDRAMto performcache
read operations during precharge and refresh cycles to mnimze
wait states and reduce power. It is only necessary to select /S and
/Gand provide the appropriate column address to read data as
shown in the table below The rowaddress of the SRAMcache
accessed wthout clocking /RE wll be specified by the LRR address
latch loaded during the last /RE active read cycle. To performa
cache read in static column mode, /CAL is held high, and the cache
contents at the specified column address wll be valid at time t
AC
after address is stable. To performa cache read in page mode,
/CAL is clocked to latch the column address. The cache data is
valid at time t
AC
after the column address is setup to /CAL.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the rowaddress supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle.
Low Power Mode
The EDRAMenters its lowpower mode when /S is high. In this
mode, the internal DRAMcircuitry is powered down to reduce
standby current to 1mA.
Low Power Self-RefreshOption
When the lowpower, self refresh mode option is specified when
ordering the EDRAM the EDRAMenters this mode when /RE is
clocked while /S, W/R, /F and /WE are high; and /CAL is low In this
mode, the power is turned off to all I/Opins except /RE to mnimze
chip power, and an on-board refresh clock is enabled to performself-
refresh cycles using the on-board refresh counter. The EDRAM
remains in this lowpower mode until /RE is brought high again to
termnate the mode. The EDRAM/RE input must remain high for t
RP2
followng exit fromself-refresh mode to allowany on-going internal
refresh to termnate prior to the next memory operation.
Write-Per-Bit Operation
The DM2212 version of the 1Mb x 4 EDRAMoffers a write-per-
bit capability which allows single bits of the memory to be selectively
written wthout altering other bits in the same word. This capability
may be useful for implementing parity or masking data in video
graphics applications. The bits to be written are determned by a
bit mask data word which is placed on the I/Odata pins DQ
0-3
prior
to clocking /RE. The logic one bits in the mask data select the bits
to be written. As soon as the mask is latched by /RE, the mask data
is removed and write data can be placed on the databus. The mask
is only specified on the /RE transition. During page mode burst
write operations, the same mask is used for all write operations.
+3.3 Volt Power Suppy Operation
If the +3.3 volt power supply option is specified, the EDRAM
wll operate froma +3.3 volt ±0.3 volt power supply and all inputs
and outputs wll have LVTTL/LVCMOS compatible signal levels. The
+3.3 volt EDRAMwll not accept input levels which exceed the
power supply voltage. If mxed I/Olevels are expected in your
system please specify the +5 volt version of the EDRAM
/CAL Before /RE Refresh(“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below
/RE Ony RefreshOperation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAMrefresh, it is possible to perform
an /RE only refresh using an externally supplied rowaddress. /RE
refresh is performed by executing a
write cycle
(W/R and /F are
high) where /CAL is not clocked. This is necessary so that the current
cache contents and LRR are not modified by the refresh operation.
All combinations of addresses A
0-9
must be sequenced every 64ms
refresh period. A
10
does not need to be cycled. Read refresh cycles
Function
/S
/G
/CAL
A
0-8
Cache Read (Static Column)
L
H
Column Address
Cache Read (Page Mode)
L
Column Address
H = High; L = Low X = Dont Care;
↓
= Transitioning
L
L
↓
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM2202T1-15L | Enhanced DRAM (EDRAM) |
| DM2202T-12 | Enhanced DRAM (EDRAM) |
| DM2202T-12I | Enhanced DRAM (EDRAM) |
| DM2202T-12L | Enhanced DRAM (EDRAM) |
| DM2202T-15 | Enhanced DRAM (EDRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM2202T1-15L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202T-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202T-12I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202T-12L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202T-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
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