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參數(shù)資料
| 型號： | DM2202J-12I |
| 英文描述： | Enhanced DRAM (EDRAM) |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存） |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 159K |
| 代理商： | DM2202J-12I |
1-23
Symbol
Parameters
Min
Max
Test Conditions
V
CC
Supply Voltage
4.75V
All Voltages Referenced to V
SS
V
IH
V
IL
I
i(L)
I
O(L)
V
OH
V
OL
OV
≤
V
IN
≤
Vcc to 0.5 Volt
O
≤
V
I/O
≤
Vcc
I
OUT
= - 5mA (-2ma For 3.3 Volt Option)
I
OUT
= 4.2mA (2ma For 3.3 Volt Option)
0.8V
10μA
0.4V
10μA
2.4V
Vss-0.5V
-10μA
-10μA
2.4V
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Level
Output Low Level
5.25V
Min
Max
L Option
3.0V
V
CC
+0.3V
0.8V
5μA
0.4V
5μA
2.0V
Vss-0
.3V
-5μA
-5μA
2.4V
3.6V
Vcc+0.5V
Symbol
Operating Current
-15 Max
Test Condition
I
CC1
Random Read
/RE, /CAL, and Addresses Cycling: t
C
= t
C
Minimum
All Control Inputs Stable
≥
V
CC
- 0.2V, Output Driven
/RE, /CAL, /WE, and Addresses Cycling: t
C
= t
C
Minimum
/CAL, /WE, and Addresses Cycling: t
PC
= t
PC
Minimum
115mA
90mA
105mA
Fast Page Mode Read
Static Column Read
Standby
Random Write
Fast Page Mode Write
180mA
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
150mA
33MHz Typ
(1)
65mA
55mA
1mA
200 μA
1mA
1mA
50mA
110mA
135mA
Notes
2, 3, 5
2, 4, 5
2, 4, 5
2, 3
2, 4
/CAL and Addresses Cycling: t
PC
= t
PC
Minimum
Addresses Cycling: t
SC
= t
SC
Minimum
(1) “33MHz Typ” refers to worst case I
expected in a systemoperating wth a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed. (2) I
is dependent on cycle rates and is measured wth CMOS levels and the outputs open. (3) I
CC
is measured wth a maximumof one address change while
/RE = V
IL
. (4) I
CC
is measured wth a maximumof one address change while /CAL = V
IH
. (5) /Gis high.
-12 Max
225mA
145mA
110mA
/S, /F, W/R, /WE, and A
0-10
at
≥
V
CC
- 0.2V
/RE and /CAL at
≤
V
SS
+ 0.2V, I/O Open
Self-Refresh
(-L Option)
I
CC7
190mA
135mA
See “Estimating EDRAM Operating Power”
Application Note
—
Average Typical
Operating Current
I
CCT
30mA
—
1
200 μA
200 μA
Electrical Characteristics
T
A
= 0 to 70°C (Commercial), -40 to 85°C (Industrial)
R1 = 828
R1 = 1178
≤
5ns
≤
5ns
VIL
VIL
GND
+ 5.0 (+3.3 Volt Option)
Output
CL = 50pf
R2 = 295
(3.3 Volt Option)
Load Circuit
Input Waveforms
VIH
VIH
(5.0 volt)
(3.3 Volt Option)
R2 = 868
(5.0 volt)
AC Test Load and Waveforms
V
IN
Timng Reference Point at V
IL
and V
IH
Ambient Operating Temperature (T
A
)
Storage Temperature (T
S
)
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Description
Ratings
Output Voltage (V
OUT
)
Power Supply Voltage (V
CC
)
Short Circuit O/P Current (I
OUT
)
- 1 ~ 7v
- 1 ~ 7v
Input Voltage (V
IN
)
- 1 ~ 7v
-40 ~ +85°C
-55 ~ 150°C
Class 1
50mA*
3.3V Option
Rating
- .5 ~ 4.6v
- .5 ~ 4.6v
- .5 ~ 4.6v
-40 ~ +85°C
-55 ~ 150°C
Class 1
20mA*
Absolute MaximumRatings
(Beyond Which Permanent Damage Could Result)
*One output at a time; short duration.
Description
Max
Pins
Input Capacitance
Input Capacitance
2pf
6pf
A0-10
/G
Input Capacitance
7pf
/CAL, /RE, W/R, /WE, /F, /S
I/O Capacitance
6pf
DQ
0-3
Capacitance
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM2202J-12L | Enhanced DRAM (EDRAM) |
| DM2202J-15 | Enhanced DRAM (EDRAM) |
| DM2202J-15I | Enhanced DRAM (EDRAM) |
| DM2202J-15L | Enhanced DRAM (EDRAM) |
| DM2202J-20 | Enhanced DRAM (EDRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM2202J-12L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202J-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202J-15I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202J-15L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2202J-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
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