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參數(shù)資料
| 型號(hào)： | DM2200J1-15L |
| 英文描述： | Enhanced DRAM (EDRAM) |
| 中文描述： | 增強(qiáng)的DRAM（eDRAM內(nèi)存） |
| 文件頁(yè)數(shù)： | 4/19頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | DM2200J1-15L |
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are not allowed because a DRAMrefresh cycle does not occur when
a read refresh address matches the LRR address latch.
IntializationCycles
A mnimumof 10 initialization (start-up) cycles are required
before normal operation is guaranteed. At least eight /F refresh
cycles and two read cycles to different rowaddresses are necessary
to complete initialization. /RE must be high for at least 300ns prior
to initialization.
UnallowedMode
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
high.
ReducedPinCount Operation
Although it is desirable to use all EDRAMcontrol pins to
optimze systemperformance, it is possible to simplify the interface
to the EDRAMby either tying pins to ground or by tying one or
more control inputs together. The /S input can be tied to ground if
the lowpower standby modes are not required. The /CAL and /F
pins can be tied together if hidden refresh operation is not
required. In this case, a CBR refresh (/CAL before /RE) can be
performed by holding the combined input lowprior to /RE. A CBR
refresh does not require that a rowaddress be supplied when /RE
is asserted. The timng is identical to /F refresh cycle timng. The
/WE input can be tied to /CAL if independent posting of column
addresses and data are not required during write operations. In
this case, both column address and write data wll be latched by
the combined input during writes. W/R and /Gcan be tied together
if reads are not performed during write hit cycles. If these
techniques are used, the EDRAMwll require only three control
lines for operation (/RE, /CAS [combined /CAL, /F and /WE], and
W/R [combined W/R and /G]). The simplified control interface still
allows the fast page read/write cycle times, fast randomread/write
times, and hidden precharge functions available wth the EDRAM
PinDescriptions
/RE — Row Enabe
This input is used to initiate DRAMread and write operations
and latch a rowaddress. It is not necessary to clock /RE to read
data fromthe EDRAMSRAMrowregisters. On read operations, /RE
can be brought high as soon as data is loaded into cache to allow
early precharge.
/CAL — ColumnAddress Latch
This input is used to latch the column address and in combination
wth /WE to trigger write operations. When /CAL is high, the column
address latch is transparent. When /CAL is low the column address
latch is closed and the output of the latch contains the address
present while /CAL was high.
W/R — Write/Read
This input along wth /F specifies the type of DRAMoperation
initiated on the lowgoing edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/F — Refresh
This input wll initiate a DRAMrefresh operation using the
internal refresh counter as an address source when it is lowon the
lowgoing edge of /RE.
/WE — Write Enabe
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low
/G— Output Enabe
This input controls the gating of read data to the output data
pins during read operations.
/S — ChpSelect
This input is used to power up the I/Oand clock circuitry
When /S is high, the EDRAMremains in its lowpower mode. /S
must remain active throughout any read or write operation. Wth
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
DQ
0-3
— Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM On the DM2212 write-per-bit memory these pins
are also used to specify the bit mask used during write operations.
A
0-10
— Mutipex Address
These inputs are used to specify the rowand column
addresses of the EDRAMdata. The 11-bit rowaddress is latched on
the falling edge of /RE. The 9-bit column address can be specified
at any other time to select read data fromthe SRAMcache or to
specify the write column address during write cycles.
V
CC
Power Suppy
These inputs are connected to the +5 or +3.3 volt power supply
V
SS
Ground
These inputs are connected to the power supply ground
connection.
1-22
Pin Names
Function
A
0-10
Address Inputs
Row Enable
Data In/Data Out
Column Address Latch
Write/Read Control
Power (+5V or +3.3V)
DQ
0-3
/CAL
W/R
V
CC
/RE
Pin Names
Function
/WE
/G
/F
/S
Chip Select - Active/Standby Control
NC
Not Connected
Write Enable
Output Enable
Refresh Control
Ground
V
SS
Pin Names
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM2200J-12 | Enhanced DRAM (EDRAM) |
| DM2200J-12I | Enhanced DRAM (EDRAM) |
| DM2200J-12L | Enhanced DRAM (EDRAM) |
| DM2200J-15 | Enhanced DRAM (EDRAM) |
| DM2200J-15I | Enhanced DRAM (EDRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM2200J-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J-12I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J-12L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J-15I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
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