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參數(shù)資料
| 型號： | DM2200J1-15 |
| 英文描述： | Enhanced DRAM (EDRAM) |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存） |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 159K |
| 代理商： | DM2200J1-15 |
coherency The EDRAMdelivers 12ns cycle page mode memory
writes. Memory writes do not affect the contents of the cache row
register except during a cache hit.
By integrating the SRAMcache as rowregisters in the DRAM
array and keeping the on-chip control simple, the EDRAMis able
to provide superior performance over standard slow4Mb DRAMs.
By elimnating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
Functional Description
The EDRAMis designed to provide optimummemory
performance wth high speed mcroprocessors. As a result, it is
possible to performsimultaneous operations to the DRAMand
SRAMcache sections of the EDRAM This feature allows the EDRAM
to hide precharge and refresh operation during SRAMcache reads
and maximze SRAMcache hit rate by maintaining valid cache
contents during write operations even if data is written to another
memory page. These newfunctions, in conjunction wth the faster
basic DRAMand cache speeds of the EDRAM mnimze processor
wait states.
EDRAMBasic Operating Modes
The EDRAMoperating modes are specified in the table below
Ht andMss Termnology
In this datasheet, “hit” and “mss” always refer to a hit or mss
to the page of data contained in the SRAMcache rowregister. This
is always equal to the contents of the last rowthat was read from
(as modified by any write hit data). Writing to a newpage does not
cause the cache to be modified.
DRAMReadHt
A DRAMread request is initiated by clocking /RE wth W/R low
and /F & /CAL high. The EDRAMcompares the newrowaddress to
the last rowread address latch (LRR - an 11-bit latch loaded on
each /RE active read mss cycle). If the rowaddress matches the
LRR, the requested data is already in the SRAMcache and no
DRAMmemory reference is initiated. The data specified by the
column address is available at the output pins at the greater of
times t
AC
or t
GQV
. Since no DRAMactivity is initiated, /RE can be
brought high after time t
RE1
, and a shorter precharge time, t
RP1
, is
allowed. It is possible to access additional SRAMcache locations by
providing newcolumn addresses to the multiplex address inputs.
Newdata is available at the output at time t
AC
after each column
address change. During read cycles, it is possible to operate in
either static column mode wth /CAL=high or page mode wth /CAL
clocked to latch the column address. In page mode, data valid
time is determned by either t
AC
or t
CQV
.
DRAMReadMss
A DRAMread request is initiated by clocking /RE wth W/R low
and /F & /CAL high. The EDRAMcompares the newrowaddress to
the LRR address latch (an 11-bit latch loaded on each /RE active
read mss cycle). If the rowaddress does not match the LRR, the
requested data is not in SRAMcache and a newrowmust be
fetched fromthe DRAM The EDRAMwll load the newrowdata
into the SRAMcache and update the LRR latch. The data at the
specified column address is available at the output pins at the
greater of times t
RAC
, t
AC
, and t
GQV
. It is possible to bring /RE high
after time t
RE
since the newrowdata is safely latched into SRAM
cache. This allows the EDRAMto precharge the DRAMarray while
data is accessed fromSRAMcache. It is possible to access additional
SRAMcache locations by providing newcolumn addresses to the
multiplex address inputs. Newdata is available at the output at time
t
AC
after each column address change. During read cycles, it is
possible to operate in either static column mode wth /CAL=high or
page mode wth /CAL clocked to latch the column address. In page
mode, data valid time is determned by either t
AC
or t
CQV
.
DRAMWrite Ht
If a DRAMwrite request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high, the EDRAMwll compare the newrow
address to the LRR address latch (an 11-bit address latch loaded
on each /RE active read mss cycle). If the rowaddress matches,
the EDRAMwll write data to both the DRAMarray and selected
SRAMcache simultaneously to maintain coherency The write
address and data are posted to the DRAMas soon as the column
address is latched by bringing /CAL lowand the write data is
latched by bringing /WE low The write address and data can be
latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for the column
address and t
DS
for the data). During a write burst sequence, the
second write data can be posted at time t
RSW
after /RE. Subsequent
writes wthin a page can occur wth write cycle time t
PC
. Wth /G
enabled and /WE disabled, it is possible to performcache read
operations while the /RE is activated in write hit mode. This allows
1-20
Function
/S
Unallowed Mode
Low Power Self-Refresh
Option
H = High; L = Low X = Dont Care;
↓
= High-to-LowTransition; LRR = Last RowRead
H
/RE
W/R
/F
A
0-10
Comment
L
X
H
X
Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock (-L Option)
H
↓
H
H
X
Internal Refresh
X
X
L
X
Cache Reads Enabled
Read Miss
L
L
H
Row
≠
LRR
DRAM Row to Cache
Write Hit
L
H
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write Miss
L
H
H
Row
≠
LRR
Write to DRAM, Cache Not Updated, Reads Disabled
↓
↓
↓
↓
Read Hit
L
L
H
/CAL
X
L
X
H
H
H
H
/WE
X
Low Power Standby
H
H
X
X
X
1mA Standby Current
H
H
H
X
X
H
H
X
Row = LRR
No DRAM Reference, Data in Cache
↓
EDRAM Basic Operating Modes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM2200J1-15I | Enhanced DRAM (EDRAM) |
| DM2200J1-15L | Enhanced DRAM (EDRAM) |
| DM2200J-12 | Enhanced DRAM (EDRAM) |
| DM2200J-12I | Enhanced DRAM (EDRAM) |
| DM2200J-12L | Enhanced DRAM (EDRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM2200J1-15I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J1-15L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J-12I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
| DM2200J-12L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced DRAM (EDRAM) |
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