參數(shù)資料
型號： DJCE6353SL9EN882128
廠商： INTEL CORP
元件分類： 接收器
英文描述： Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV)
中文描述： VIDEO DISCRIMINATOR, QFP64
封裝： LQFP-64
文件頁數(shù)： 17/26頁
文件大小： 322K
代理商： DJCE6353SL9EN882128
CE6353
Data Sheet
17
Intel Corporation
Parameter
Symbol
Value
Unit
Min.
Max.
CLK clock frequency (Primary)
f
CLK
0
400
1
1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.
2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
kHz
Bus free time between a STOP and START condition.
t
BUFF
200
ns
Hold time (repeated) START condition.
t
HD;STA
200
ns
LOW period of CLK clock.
t
LOW
1300
ns
HIGH period of CLK clock.
t
HIGH
600
ns
Set-up time for a repeated START condition.
t
SU;STA
200
ns
Data hold time (when input).
t
HD;DAT
100
ns
Data set-up time
t
SU;DAT
100
ns
Rise time of both CLK and DATA signals.
t
R
note
2
ns
Fall time of both CLK and DATA signals, (100 pF to ground).
t
F
20
ns
Set-up time for a STOP condition.
t
SU;STO
200
ns
Table 3 - Timing of 2-Wire Bus
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