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| 型號(hào)： | DIV100 |
| 英文描述： | DIV100 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| 中文描述： | DIV100 -已停產(chǎn)產(chǎn)品。不再推薦用于新設(shè)計(jì)。 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | DIV100 |
7
DIV100
As an example of how to use this model, consider this
problem:
Determine the highest ambient temperature at which the
DIV100 may be operated with a continuous short circuit
to ground. V
CC
=
±
15VDC.
P
D(MAX)
= 600mW. T
J(MAX)
= +175
°
C.
T
A
= T
J(MAX)
– P
DQ
(
θ
2
+
θ
3
) – P
DX(SHORT – CIRCUIT)
(
θ
1
+
θ
2
+
θ
3
)
= 175
°
C – 18
°
C – 119
°
C = 38
°
C
P
D(ACTUAL)
= P
DQ
+ P
DX(SHORT – CIRCUIT)
≤
P
D(MAX)
= 255mW + 345mW = 600mW
The conclusion is that the device will withstand a short-
circuit up to T
= +38
°
C without exceeding either the 175
°
C
or 600mW absolute maximum limits.
LIMITING OUTPUT VOLTAGE SWING
The negative output voltage swing should be limited to
±
11V, maximum, to prevent polarity inversion and possible
system instability. This should be done by limiting the input
voltage range.
THEORY OF OPERATION
The DIV100 is a log-antilog divider consisting of four
operational amplifiers and four logging transistors inte-
grated into a single monolithic circuit. Its basic principal of
operation can be seen by an analysis of the circuit in Figure
4.
The logarithmic equation for a bipolar transistor is:
V
BE
= V
T
n (I
C
/I
S
),
where: V
T
= kT/q
k = Boltzmann’s constant = 1.381
x
10
–23
T = Absolute temperature in degrees Kelvin
q = Electron charge = 1.602
x
10
–19
I
C
= Collector current
I
S
= Reverse saturation current
FIGURE 2. Overload Protection Circuit.
tion. No other overload protection circuit is necessary.
Inputs are internally protected against overvoltages and they
are current-limited by at least a 10k
series resistor. The
output is protected against short circuits to power supply
common only.
STATIC SENSITIVITY
No special handling is required. The DIV100 does not use
MOS-type transistors. Furthermore, all external leads are
protected by resistors against low energy electrostatic dis-
charge (ESD).
INTERNAL POWER DISSIPATION
Figure 3 is the thermal model for the DIV100 where:
P
DQ
= Quiescent power dissipation
= |+V
CC
| I
+QUIESCENT
+ |–V
CC
| I
–QUIESCENT
P
DX
= Worst case power dissipation in the output
transistor
= V
CC2
/4R
LOAD
(for normal operation)
= V
I
(for short-circuit)
T
= Junction temperature (output loaded)
T
J
* = Junction temperature (no load)
T
C
= Case temperature
T
A
= Ambient temperature
θ
= Thermal resistance
This model is a multiple power source model to provide a
more accurate simulation.
The model in Figure 3 must be used in conjunction with the
DIV100’s absolute maximum ratings of internal power dis-
sipation and junction temperature to determine the derated
power dissipation capability of the package.
(1)
DIV100
+V
CC
–V
CC
FIGURE 3. DIV100 Thermal Model.
P
DQ
P
DX
T
C
3
= 50°C/W
θ
T
A
T
J
*
T
J
1
= 275°C/W
θ
2
= 20°C/W
θ
FIGURE. 4 One-Quadrant Log-Antilog Divider.
V
O
Q
1
Q
4
Q
2
Q
3
V
REF
V
N
R
X
R
N
R
O
R
D
V
D
V
1
V
3
V
2
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