I N T E R N A L A R C H I T E C T U R E D E TA I L S
The DMN-8600 can accomplish very compute-inten-
sive signal processing tasks because it integrates multiple
high-performance processing modules on a single chip.
R I S C E n g i n e
Two 32-bit SPARC processors perform all of the
following functions: system processing, audio processing,
and high-level flow control and and decision-making tasks
for video processing, and 2D graphics processing.
V i d e o D S P
As a highly integrated processor engine, the
DMN-8600 is designed to implement motion-compensated,
block-DCT-based video compression algorithms. To this end,
the DMN-8600 includes a video DSP and motion estimation
(ME) coprocessor that off-loads compute-intensive tasks from
the SPARC processors.
M o t i o n E s t i m a t i o n C o p r o c e s s o r
The programmable ME coprocessor has a throughput
of 29 billion arithmetic operations per second (BOPS). It takes
the ME commands from the SPARC processor and generates
results for each target.
V i d e o D S P C o p r o c e s s o r
The video DSP coprocessor performs vector memory-
to-memory instructions. This improves code density and
off-loads the SPARC processors. Its 64 Kbyte data memory
is double-buffered (two banks) to allow concurrent DMA
and DSP operations. Some of the functions that the DSP
coprocessor performs include: de-telecine, activity measures,
motion compensation, adaptive temporal and de-interlace
filtering, linear filtering/decimation, DCT/IDCT (up to 12
bits), quantization/dequantization, and variable length
encoding/decoding. The video DSP coprocessor operates
at approximately 16 BOPS.
A u d i o P r o c e s s i n g
The audio processing hardware is physically inte-
grated into each SPARC processor. The hardware consists of
two parallel 64-bit MAC units with 32-bit precision, and a
DSP instruction set to support efficient encoding and decod-
ing of a wide variety of audio algorithms, including MPEG-1
Layer 2, DTS, MP3, Dolby Digital
In addition, audio special effects such as 3D audio, Dolby
ProLogic
, echo, harmonizing, bass management, FIR and IIR
filters are supported. Each SPARC processor can execute two
instructions in parallel, a MAC operation (DSP instruction)
and a regular SPARC processor instruction.
TM
, AAC, MLP, and WMA.
P r o g r a m m a b i l i t y
The DMN-8600 is compatible with LSI Logic’s
proprietary C-Ware SW develoment environment.
C-Ware is an object oriented software architecture that
abstracts the underlying hardware. This promotes portability
and application re-usability within and across LSI Logic’s
product families. Figure 4 shows the basic C-Ware architec-
ture and how it supports cross-product compatibility.
Audio / Video IF
Motion
Estimation
29 BOPS
Generic Host
1394 Link IF
SDRAM
TMEM
WMEM
DMEM
(16 KB)
I Cache
(16 KB)
I Cache
(16 KB)
RMEM
Video DSP
16 BOPS
AMEM
RISC CPU
&
Audio DSP
RISC CPU
&
Audio DSP
150 MIPS
150 MIPS
Storage IF
SIO
32-bit Bus
SDR/DDR SDRAM
8 MB - 64 MB
16/32-bit generic host
DVD - RX
IEEE1394 PHY
YUV video inputs
YUV video output
8-channel audio_out
4-channel audio_in
Dual UARTs
IR Rx/TX
SPI
IDC
Figure 3: DMN-8600 Architecture