參數(shù)資料
型號: DG542DJ-E3
廠商: Vishay Siliconix
文件頁數(shù): 18/18頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16DIP
標(biāo)準(zhǔn)包裝: 500
功能: 視頻開關(guān)
電路: 4 x SPST - NC/NO
導(dǎo)通狀態(tài)電阻: 60 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 10 V ~ 18 V,±10 V ~ 15 V
電流 - 電源: 3.5mA
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
Document Number: 70055
S11-1429–Rev. H, 18-Jul-11
www.vishay.com
9
Vishay Siliconix
DG540, DG541, DG542
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATIONS
Power Supplies
A useful feature of the DG54X family is its power supply
flexibility. It can be operated from a single positive supply
(V+) if required (V- connected to ground).
Note that the analog signal must not exceed V- by more than
- 0.3 V to prevent forward biasing the substrate p-n junction.
The use of a V- supply has a number of advantages:
1.
It allows flexibility in analog signal handling, i.e., with
V- = - 5 V and V+ = 12 V; up to ± 5 V ac signals can
be controlled.
2.
The value of on capacitance [CS(on)] may be reduced.
A property known as ‘the body-effect’ on the DMOS
switch devices causes various parametric effects to
occur. One of these effects is the reduction in CS(on)
for an increasing V body-source. Note, however, that
to increase V- normally requires V+ to be reduced
(since V+ to V- = 21 V max.). Reduction in V+ causes
an increase in RDS(on), hence a compromise has to
be achieved. It is also useful to note that optimum
video linearity performance (e.g., differential phase
and gain) occurs when V- is around - 3 V.
3.
V- eliminates the need to bias the analog signal using
potential dividers and large coupling capacitors.
Decoupling
It is an established RF design practice to incorporate
sufficient bypass capacitors in the circuit to decouple the
power supplies to all active devices in the circuit. The
dynamic performance of the DG54X is adversely affected by
poor decoupling of power supply pins. Also, of even more
significance, since the substrate of the device is connected
to the negative supply, adequate decoupling of this pin is
essential.
Rules:
1.
Decoupling capacitors should be incorporated on all
power supply pins (V+, V-). (See Figure 7.)
2.
They should be mounted as close as possible to the
device pins.
3.
Capacitors
should
have
good
high
frequency
characteristics - tantalum bead and/or monolithic
ceramic types are adequate.
Suitable decoupling capacitors are 1- to 10 F
tantalum bead, plus 10- to 100 nF ceramic.
Board Layout
PCB layout rules for good high frequency performance must
be observed to achieve the performance boasted by the
DG540. Some tips for minimizing stray effects are:
1.
Use extensive ground planes on double sided PCB,
separating adjacent signal paths. Multilayer PCB is
even better.
2.
Keep signal paths as short as practically possible,
with all channel paths of near equal length.
3.
Careful arrangement of ground connections is also
very important. Star connected system grounds
eliminate signal current flowing through ground path
parasitic resistance from coupling between channels.
Figure 7. Supply Decoupling
+
- 3 V
GNDs
+ 15 V
DG540
V+
V-
S1
S2
S3
S4
D1
D2
D3
D4
C1
C2
C1
C2
C1 = 10 μF Tantalum
C2 = 0.1 μF Ceramic
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