參數(shù)資料
型號: DG445ETE+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 開關(guān)
電路: 4 x SPST - NO
導(dǎo)通狀態(tài)電阻: 160 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 10 V ~ 30 V,±4.5 V ~ 20 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(5x5)
包裝: 帶卷 (TR)
DG444/DG445
Improved, Quad, SPST Analog Switches
6
_______________________________________________________________________________________
tOFF
0.8 x VOUT
VOUT
0.8 x VOUT
tf < 20ns
tr < 20ns
50%
0V
+3V
SWITCH
OUTPUT
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
tON
SWITCH
INPUT
LOGIC
INPUT
+3V
IN
+5V
V-
-15V
(
)
RL
CL
VOUT
S
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
GND
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
VOUT = VD
RL
RL + rDS(ON)
LOGIC
INPUT
VL
+15V
V+
D
DG444
DG445
Figure 2. Switching Time
Applications Information
General Operation
Switches are open when power is off.
IN, D, and S should not exceed V+ or V-, even with
the power off.
Switch leakage is from each analog switch terminal
to V+ or V-, not to other switch terminals.
Operation with Supply Voltages
Other than ±15V
Using supply voltages other than ±15V will reduce the
analog signal range. The DG444/DG445 switches oper-
ate with ±4.5V to ±20V bipolar supplies or with a +10V
to +30V single supply; connect V- to 0V when operating
with a single supply. Also, all device types can operate
with unbalanced supplies such as +24V and -5V. VL
must be connected to +5V to be TTL compatible, or to
V+ for CMOS-logic level inputs. The Typical Operating
Characteristics graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
VL , V-, and logic inputs. If power-supply sequenc-
ing is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
V+
D
V-
S
Vg
Figure 1. Overvoltage Protection Using External Blocking Diodes
_____________________Pin Description
PIN
DIP/SO
THIN QFN
NAME
FUNCTION
1, 16, 9, 8
15, 14, 7, 6
IN1–IN4
Logic Control
Inputs
2, 15, 10, 7
16, 13, 8, 5
D1–D4
Drain Outputs
3, 14, 11, 6
1, 12, 9 4
S1–S4
Source Outputs
42
V-
Negative-Supply
Voltage Input
53
GND
Ground
12
10
VL
Logic-Supply
Voltage Input
13
11
V+
Positive-Supply-
Voltage
Input—Connected
to Substrate
—EP
PAD
Exposed Pad
Connect Pad to V+
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