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參數資料
| 型號： | DF3069RX25WV |
| 廠商： | Renesas Electronics America |
| 文件頁數： | 3/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC H8/3069R MCU FLASH 100TQFP |
| 產品培訓模塊： | RX 12-Bit ADC RX Bus State Controller RX Low Voltage Detection and Reset Sources RX Watchdog Timer RX 10-Bit ADC |
| 標準包裝： | 1 |
| 系列： | H8® H8/300H |
| 核心處理器： | H8/300H |
| 芯體尺寸： | 16-位 |
| 速度： | 25MHz |
| 連通性： | SCI，智能卡 |
| 外圍設備： | DMA，PWM，WDT |
| 輸入/輸出數： | 70 |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數據轉換器： | A/D 8x10b; D/A 2x8b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
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Peripherals
H8 Peripherals
9
■ DMA Controller (DMAC)
Max. of 4 channels can be used
Dual-address or single-address
mode can be selected
Supports Single, Burst, Sequential,
Idle and Repeat Transfer modes
Data can be transferred in word
or byte units
Activation: internal interrupt,
external request, auto-request
■ Data Transfer Controller (DTC)
Max. of 85 channels can be used
Multiple transfers or multiple
types of transfers possible for
one activation source
Supports Single, Burst, Chain and
Repeat Transfer modes
Data can be transferred in byte or
word units
Activation sources: interrupt and
software
■ External DMA Controller
(ExDMAC)
Max. of 4 channels can be used
Selection of byte or word transfer
data length
Transfer data in parallel with CPU
or other internal bus master
Dual-address or single-address
mode can be selected
Supports Single, Burst, Sequential,
Idle and Repeat Transfer modes
Data can be transferred in word
or byte units
Activation: internal interrupt,
external request, auto-request
DTC
service
request
Interrupt
controller
On-chip 1KB RAM
Channel n
Interrupt
request
n + 1
n + 2
Source
Memory data
Destination
DMA Register
Source
Serial I/O
Destination
Memory
Data Transfer Controller: Chain Transfer Mode
Address bus
A15 to A0
Exter
nal
memory
Exter
nal
device
(Read)
(Write)
Address bus
Data
bu
s
RD
HWR, LWR
A23 to A0
H8S/2633
DACK
Single-Address Mode
(Parallel read and write)
Exter
nal
memory
Exter
nal
device
Read (1st cycle)
RD
HWR, LWR
H8S/2633
Dual-Address Mode
(Two-cycle read and write)
Address bus
A23 to A0
BUFFER
D15 to D0
Write (2nd cycle)
Data
bu
s
D15 to D0
DMA Controller Block Diagram
ExDMA Controller Block Diagram
Data flow
External
address bus
External
data bus
EXDMAC
EDACK
EDREQ
External
memory
External device
with DACK
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