參數(shù)資料
型號(hào)： DEM-DDC112U-C
英文描述： DEM-DDC112U-C - Evaluation Fixture
中文描述： DEM的DDC112U - C部分-評(píng)估夾具
文件頁(yè)數(shù)： 6/13頁(yè)
文件大?。?/td> 194K
代理商： DEM-DDC112U-C
6
DEM-DAI
DIGITAL AUDIO TRANSMITTER FLAGS
Switch SW9 is a DIP switch used to setup additional digital
audio transmitter options. Figure 4 shows an illustration of
SW9, with each switch labeled with its appropriate designa-
tor. The following paragraphs explains the function of each
of the DIP switch segments.
The PRO switch is used to select Consumer or Professional
mode. Set this switch HIGH for Consumer mode, and LOW
for Professional mode. This pin should also be set LOW
when using the transmitter in Transparent mode.
The PRO switch selection, either Consumer or Professional,
defines the function of the next seven switches. For most
DEM-DAI applications, set the mode to Consumer (PRO =
HIGH). Only the consumer definitions are given here. Con-
sult the CS8402A data sheet for information regarding the
Professional mode definitions.
FC0 and FC1, corresponding to channel status bits 24 and
25, denote the sampling frequency. Table IV shows the
switch settings and their corresponding selections.
FC0
FC1
SAMPLING FREQUENCY
0
0
1
1
0
1
0
1
44.1kHz
48kHz
32kHz
44.1kHz (CD submode)
TABLE IV. Sampling Frequency Flag Settings.
The remaining five switches correspond to channel status bit
selections. C2, C3, C8,C9, and C15 correspond to channel
status bits 2, 3, 8, 9, and 15. Consult the AES specification
or the CS8402A data sheet for the definition of these bits in
Consumer and Professional modes.
JUMPERS
There are six jumpers that are used to setup clocking
options. They are described in the following paragraphs.
JP1 is used to select the system clock source. Figure 5 shows
the header block with descriptions for each of the three
options.
FIGURE 5. System Clock Source Selection.
JP2 is used to select the bit clock (BCK) source. Figure 6
shows the header block with descriptions for each of the four
options. Regardless of the BCK source selected, the bit
clock rate will be 64 f
S
.
FIGURE 6. Bit Clock Source Selection.
FIGURE 4. Digital Audio Transmitter Status Bit Switch.
SW9
L
H
C9
C8
C15
C2
C3
FC0
FC1
PR0
Channel
Status
Bit
Selection
H = Consumer Mode
L = Professional Mode
In consumer mode, these correspond to channel status
bits 24 and 25, which denote the sampling frequency.
JP1
INV
NML
XTAL
Inverted output clock from digital audio receiver
Normal output clock from digital audio receiver
Use crystal oscillator/divider as system clock
JP2
DIR
512
384
256
BCK generated by digital audio receiver
BCK from crystal oscillator/divider, system clock = 512 f
S
BCK from crystal oscillator/divider, system clock = 384 f
S
BCK from crystal oscillator/divider, system clock = 256 f
S
NOTE: Regardless of selection, BCK = 64 f
S
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