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參數(shù)資料
| 型號： | DEM-DDC101P-C |
| 英文描述： | DEM-DDC101P-C - DISCONTINUED PRODUCT. No longer recommended for new design. |
| 中文描述： | DEM的DDC101P - C部分-已停產(chǎn)產(chǎn)品。不再推薦用于新設(shè)計。 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 194K |
| 代理商： | DEM-DDC101P-C |
9
DEM-DAI
Figure 14 shows the ADC Master configuration. The ADC
generates all of the serial interface clocks in this configura-
tion. The system clock is derived from the crystal oscillator/
divider circuit. The clocks and data from the ADC are routed
to the CS8402A and transmitted as a S/PDIF data stream at
both optical (U10) and RCA (J2) connectors.
FIGURE 14. ADC Master Configuration.
Table VIII shows the DEM-DAI board switch and jumper
configurations for ADC Master configuration.
SWITCH/JUMPER
CONFIGURATION
SW1, SW2, SW3
Setup to match the SW4, SW5, and SW6
settings.
SW4, SW5, SW6
Setup to match the corresponding ADC data
format.
SW7
Set to Master mode.
SW9
PRO = H; FC0 and FC1 = sample rate in use;
all others = L.
JP1
Set to XTAL.
JP2
Remove jumper.
JP3
Remove jumper.
JP4
Set to 256/512 f
S
or 384 f
S
.
Set to 384 f
, 512 f
S
, or DIR1 (for 256 f
S
XTAL operation).
JP5
JP6
Set to NML.
STEREO AUDIO CODEC
Figure 15 shows the CODEC configuration. In this mode,
the CS8412 is used to recover the audio clocks and data from
a S/PDIF data stream. The clocks are supplied to the CODEC
and the CS8402A transmitter. Data flows from the CS8412
receiver to the CODEC data input, and from the CODEC
data output to the CS8402A transmitter.
FIGURE 15. CODEC Configuration.
Table IX shows the DEM-DAI board switch and jumper
configurations for CODEC configuration.
SWITCH/JUMPER
CONFIGURATION
SW1, SW2, SW3
Setup to match the corresponding CODEC
input data format.
SW4, SW5, SW6
Setup to match the corresponding CODEC
output data format.
SW7
Set to Slave mode.
SW9
PRO = H; FC0 and FC1 = sample rate in use;
all others = L.
JP1
Set to NML.
JP2
Set to DIR.
JP3
Set DIR.
JP4
Not used, but set to 256/512 f
S
.
JP5
Set to DIR1.
JP6
Set NML.
TABLE VIII. Switch and Jumper Settings for ADC Master
Configuration.
TABLE IX. Switch and Jumper Settings for ADC Master
Configuration.
XTAL OSC
(256/384/512f
S
)
CS8402A
Analog
Input
DEM-PCM
Evaluation
Board
SYSCLK
LRCK
BCK
Data
CS8412
Analog
Input
DEM-PCM
Evaluation
Board
CS8402A
LRCK, BCK
LRCK
BCK
Data
SYSCLK
Data
Analog
Output
2nd-Order
Post LPF
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