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參數(shù)資料
| 型號(hào)： | DEM-ADS1201U |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USING THE ADS1201 EVALUATION BOARD(ADS1201評估板的使用) |
| 中文描述： | 使用本ADS1201評估板（ADS1201評估板的使用） |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 741K |
| 代理商： | DEM-ADS1201U |
2
INSTALLATION
The ADS1201U evaluation kit contains the following items:
A completely assembled and tested ADS1201U Evalua-
tion Board
25-pin ribbon cable with connectors (PC Parallel Port
Interface Cable)
A 3 1/2
"
setup diskette containing all software compo-
nents needed to install and run the ADS1201U demonstra-
tion software
ADS1201U Application Bulletin
ADS1201U Product Data Sheet
The following system requirements are needed in order to
install and run the ADS1201U evaluation software:
IBM-compatible PC with a 486/66MHz processor or
better, Super VGA graphics, bi-directional parallel port
and Microsoft Windows 3.1 or higher operating system
Triple DC power supply (+5V,
±
15V)
A clean signal source
To install the ADS1201U demonstration board, first verify
that the power supply is set to +5V and
±
15V DC. Make
sure that the ADS1201 modulator is properly inserted in the
socket with correct orientation (see component layout in
Figure 18). Connect the power cables to the board and turn
the power on. The LED close to the Xilinx FPGA should
turn on for a short period and then go off. This will indicate
that the Xilinx is configured properly. Next, connect the 25-
pin ribbon cable between the board and the PC parallel port.
Connect the input signal via a coaxial cable to the BNC
connector on the board marked as J1. Make sure that the
input signal does not exceed the maximum input range of
the ADS1201 modulator.
The ADS1201 evaluation software is written in Visual
Basic. To install the ADS1201 evaluation software, insert
the 3 1/2
"
diskette supplied with the demo kit into the PC
floppy drive A and run the SETUP.EXE program from drive
A. This will automatically install all the necessary software
components in appropriate locations on drive C. It also
creates a directory on drive C called “ADS1201demo” and
installs the ADS1201DEMO.EXE in that directory. The
user can create a shortcut to this program, or run the
program directly from this directory.
HARDWARE DESCRIPTION
Figure 15 shows the schematic of the evaluation board.
Figure 16 and 17 shows the digital filter and control cir-
cuitry inside the Xilinx FPGA. The modulator clock and
decimation ratio can be programmed by setting appropriate
registers inside the FPGA. The 4MHz master oscillator is
divided down by the value in the configuration register to
produce modulator clock (MCLK). The ADS1201U evalu-
ation board is made up of the following five sections:
1) Xilinx XC4010E FPGA containing the digital filter, PC
interface and control circuitry
2) Analog input buffers
3) Input reference voltage source
4) An easy-to-use socket for ADS1201U evaluation
5) Power supply circuits
The main purpose of the analog input buffer is to convert a
single-ended signal into a differential signal with common-
mode voltage fixed at 2.5V. Jumpers JMP1 through JMP4
will allow the users to either use the on-board input buffer
or to connect an external signal directly to the input of
ADS1201U. Optionally, the users can design their own
analog input buffer in the analog breadboard area of the
board. Figure 3 shows the schematic of the analog input
buffer.
An on-board 2.5V reference voltage source is provided that
can be connected to the ADS1201U REF
IN
pin via JMP6.
Optionally, the ADS1201U can be operated from the inter-
nal reference voltage. To use the ADS1201U internal refer-
ence voltage, set jumper JMP8 to +5V and install JMP5.
The ADS1201U socket has been selected specially to allow
for easy insertion and removal of the parts under evaluation.
A low profile socket can also be used to minimize the noise
pickup at the inputs.
No power should be applied to the
DUT board while inserting new parts for evaluation.
DIGITAL FILTER DESIGN
The digital filter structure chosen to decode the output of the
Σ
modulator is a
SINC
3
digital filter. The function of the
SINC
3
digital filter is to output after each
N
input samples
a word which represents a weighted average of the last
3(N-1)+1
input samples. This filter can be implemented in
software using straight linear convolution as:
(1)
where,
x(i)
denotes the input data stream made up of ones
and zeros,
h(n)
are the filter coefficients,
y(k)
represents the
decimated output data words and
N
is the decimation ratio.
The coefficients of the digital filter,
h(n)
, are calculated
based on the desired decimation ratio as follows:
(2)
(3)
(4)
The transfer function of a
SINC
3
digital filter can be ex-
pressed as:
(5)
y( )
h n x n
( ) (
0
k
n
)
= ∑
=
1
h( )
n n
(
n
N
)
=
+
≤
≤
1
2
1
h( )
N N
(
n
N
N
n
N
n
N
)
(
)(
)
=
+
+
+
1
≤
≤
1
2
2
2
h( )
N
n
N
n
N
n
N
(
)(
)
=
≤
≤
3
1 3
2
2
3
H( )
=
N
Z
N
Z
Z
i
i
N
N
∑
=
1
1 1
1
0
1
3
1
3
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