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參數(shù)資料
| 型號： | DDX2000 |
| 英文描述： | Amplifier chipset |
| 中文描述： | 放大器芯片 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 538K |
| 代理商： | DDX2000 |
____________ DDX-2000/2060
11
Details are subject to change without notice.
VDATA/DN and is latched on the rising edge of
the VCLK/UP input as shown in Figure 4. After
all eight bits are received VMODE must be
brought high to latch the volume register. Note,
each channel volume register must be written
independently, (see Table 1).
For applications that provide digital volume
control prior to the DDX-2000, the attenuation
register can be set to 0 dB by pulling both the
VCLK/UP and VDATA/DN to ground, leaving
VMODE high.
The DDX-2000 includes an anti-clipping function
to improve audio quality when using the internal
volume control set to greater than 0 dB. This
function dynamically adjusts the volume level to
significantly reduce distortion associated with
signal clipping. This function is enabled by
setting the anti-clipping enable (ACE) pin high.
When enabled, the maximum distortion will be
limited
regardless
of
applications where maximum power is desired,
the ACE may be disabled and the output power
and distortion will increase for volume settings
which exceed 0 dB.
System Clocking
The DDX-2000 operates from a master clock
source whose frequency is 256 times the input
LRCLK sample rate (256*fs). The device can
accommodate sample rates from below 32 kHz
to above 48 kHz. Either external clock sources
or the built in oscillator may be used.
In designs that recover the clock (e.g., S/PDIF),
the 256*fs output can be utilized for the master
system clock to provide synchronous operation.
For systems that operate asynchronously, i.e.,
the crystal clock is not exactly matched to the
incoming serial data stream, the DDX-2000 will
automatically accommodate sample frequency
mismatch up to 0.2 %.
The accuracy of the master input clock will
determine amplifier system performance. To
meet the specified performance, random clock
jitter must be less than 400pS p-p.
DDX Output Control
Asserting the MUTE input (logic-high), the DDX-
2000 will command the zero state (load
damping) which short-circuits the load to
ground. The device also includes an automatic
the
volume.
For
mute function which is activated upon receipt of
2048 consecutive zero data words on both the
left and right serial inputs. Automatic transition
from mute will occur on the first non-zero input
word.
DDX-2060 POWER DEVICE
The DDX-2060 Power Device is a dual channel
H-Bridge that can deliver over 35 watts per
channel of audio output power. The DDX-2060
includes; a logic interface, integrated bridge
drivers, high efficiency MOSFET outputs and
protection circuitry. Two logic level signals per
channel are used to control high-speed
MOSFET switches to connect the speaker load
to the input supply or to ground in a bridge
configuration, according to Apogee's patented
damped ternary PWM. The DDX-2060 includes
over-current,
thermal,
protection and under-voltage lockout with
automatic recovery. A thermal warning status is
also provided.
and
over-voltage
Figure 2 - DDX-2060 Block Diagram
Logic Interface and Decode
The DDX-2060 power outputs are controlled
using two logic level timing signals. In order to
provide a proper logic interface, the VL input
must operate from the DDX-2000 logic supply.
Protection Circuitry
The DDX-2060 includes protection circuitry for
over-current, over-voltage, and thermal overload
conditions. A thermal warning pin TWARN is
activated low (open-drain MOSFET) when the IC
temperature exceeds 130°C, in advance of the
thermal shutdown protection. When a fault
condition is detected (logical OR of over-current,
over-voltage, and thermal), an internal fault
Logic I/F
and Decode
Left
H-Bridge
Protection
Circuitry
INL[1:2]
INR[1:2]
VL
PWRDN
TRI-STATE
OUTPL
FAULT
TWARN
OUTNL
OUTPR
OUTNR
Regulators
Right
H-Bridge
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDX2060 | Amplifier chipset |
| DE2812C | Fixed Inductors for Surface Mounting |
| DEM-DAI | DEM-DAI - EVALUATION FIXTURE |
| DEM-DAI1600 | DEM-DAI1600 - Evaluation Fixture |
| DEM-DAI1704 | DEM-DAI1704 - Evaluation Fixture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDX2001 | 制造商:APOGEE TECHNOLOGY 功能描述:DDX CONTROLER - LEAD FREE |
| DDX2001-13TR | 制造商:APOGEE TECHNOLOGY 功能描述:DDX CONTROLER - LEAD FREE |
| DDX2050-13TR | 制造商:APOGEE TECHNOLOGY 功能描述:Quad Power Half-Bridge. 2x40W, 8 Ω |
| DDX2052-TR | 制造商:APOGEE TECHNOLOGY 功能描述:DDX POWER DEVICE - Mini Pack - LEAD FREE |
| DDX2060-13TR | 制造商:APOGEE TECHNOLOGY 功能描述:Quad Power Half-Bridge. 2x45W, 8 Ω |
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