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參數(shù)資料
| 型號(hào)： | DDTA142TE-7-F |
| 廠商： | DIODES INC |
| 元件分類： | 功率晶體管 |
| 英文描述： | PNP PRE-BIASED 100 mA SOT-523 SURFACE MOUNT TRANSISTOR |
| 中文描述： | 100 mA, 40 V, PNP, Si, SMALL SIGNAL TRANSISTOR |
| 封裝： | GREEN, PLASTIC PACKAGE-3 |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | DDTA142TE-7-F |
DS30405 Rev. 5 - 2
1 of 3
DDTA (LO-R1) E
www.diodes.com
Diodes Incorporated
DDTA (LO-R1) E
PNP PRE-BIASED 100 mA SOT-523
SURFACE MOUNT TRANSISTOR
Epitaxial Planar Die Construction
Complementary NPN Types Available
(DDTC)
Built-In Biasing Resistors
Lead Free/RoHS Compliant (Note 2)
Features
Maximum Ratings
@ T
A
= 25 C unless otherwise specified
A
M
J
L
D
B C
H
K
G
N
TOP VIEW
Mechanical Data
Case: SOT-523
Case Material: Molded Plastic. UL Flammability
Classification Rating 94V-0
Moisture sensitivity: Level 1 per J-STD-020C
Terminals: Finish
Matte Tin Solderable per
MIL-STD-202, Method 208
Lead Free Plating (Matte Tin Finish annealed over Alloy
42 leadframe).
Terminal Connections: See Diagram
Marking: Date Code and Type Code, See Page 2
Weight: 0.002 grams (approximate)
Ordering Information (See Page 2)
P/N
R1 (NOM) R2 (NOM) Type Code
0.22K
0.47K
0.22K
0.47K
OPEN
DDTA122LE
DDTA142JE
DDTA122TE
DDTA142TE
10K
10K
OPEN
P81
P82
P83
P84
Characteristic
Symbol
V
CC
Value
-50
+5 to -6
+5 to -6
Unit
V
Supply Voltage, (2) to (3)
Input Voltage, (1) to (2)
DDTA122LE
DDTA142JE
DDTA122TE
DDTA142TE
V
IN
V
Input Voltage, (2) to (1)
V
EBO (MAX)
-5
V
Output Current All
Power Dissipation (Note 1)
Thermal Resistance, Junction to Ambient Air (Note 1)
Operating and Storage and Temperature Range
I
C
P
d
R
JA
T
j
, T
STG
-100
150
625
mA
mW
C/W
C
-55 to +150
SOT-523
Min
Dim
A
B
C
D
G
H
J
K
L
M
N
Max
Typ
0.15
0.30
0.22
0.75
0.85
0.80
1.45
1.75
1.60
0.50
0.90
1.10
1.00
1.50
1.70
1.60
0.00
0.10
0.05
0.60
0.80
0.75
0.10
0.30
0.22
0.10
0.20
0.12
0.45
0.65
0.50
0
8
All Dimensions in mm
Notes: 1. Mounted on FR4 PC Board with recommended pad layout at http://www.diodes.com/datasheets/ap02001.pdf.
2. No purposefully added lead.
N
R1
OUT
B
C
E
R2
3
2
1
IN
GND(+)
Schematic and Pin Configuration
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