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參數(shù)資料
| 型號(hào)： | DDR110-XXT7RL |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DOUBLE DATA RATE TERMINATION NETWORK WITH DISABLE SWITCH |
| 中文描述： | 雙倍數(shù)據(jù)速率終端網(wǎng)絡(luò)具有禁用開(kāi)關(guān) |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大小： | 49K |
| 代理商： | DDR110-XXT7RL |
1/5
DDR110-xxT7RL
May 2001 - Ed: 2
DOUBLE DATA RATE TERMINATION
NETWORK WITH DISABLE SWITCH
I
10 bits Termination Network.
I
Integrated Termination resistor (Rs)
I
Enable input TTL level compatible
I
Impedance matching ± 2% (A0-B0 / An-Bn)
I
Optimized
Low
Termination to Vtt.
I
Optimized Low propagation delay
Crosstalk
for
parallel
FEATURES AND BENEFITS
The DDR110 provides 10 bits resistor Network to
be used for SDR/DDR (double data rate) SDRAM
bus Termination.
This device has a series resistors (Rs) to reduce
signal reflection noise. This eliminates the need for
external terminating resistors.
The DDR Termination Nerwork is enabled with the
output Enable pin (OE). When OE is HIGH Inputs
are connected to Outputs (A connected to B).
When OE is LOW every inputs are in High
impedance state (Hi - Z).
The DDR Termination Network is a bidirectional
device when the internal switch is ON. When the
switch is OFF, the device will block current in both
directions.
This device is made using ST IPAD
TM
(Integrated
Passive & Active devices) technology.
DESCRIPTION
ASD
IPAD Computer
DDR (double data rate) Termination Network used
on.
I
Motherboard
I
Workstation
I
Server
I
Notebooks
MAIN APPLICATION
1
24
12
TSSOP24
Rs
A0
B0
VSS
VCC
OE
NC
Rs
A5
B5
Rs
A2
B2
Rs
A3
B3
Rs
A1
B1
Rs
A6
B6
Rs
A7
B7
Rs
A8
B8
Rs
A9
B9
Rs
A4
B4
GATE
CONTROL
1
24
12
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