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參數(shù)資料
| 型號： | DDC114YK |
| 廠商： | Diodes Inc. |
| 英文描述： | NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR |
| 中文描述： | npn型預偏置信號小的SOT - 26表面貼裝晶體管雙 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大小： | 389K |
| 代理商： | DDC114YK |
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SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
23
CLK
DVALID
DCLK
DIN
t
18
t
19
t
21
t
20
t
20
t
22
t
23
DOUT
Input A
MSB
Input A
LSB
Input B
MSB
Input F
LSB
Input G
MSB
Input K
LSB
Input L
MSB
Input L
LSB
Input A
MSB
Figure 22. Timing Diagram When Using the DIN Function of the DDC114
Table 11. Timing for the DDC114 Data Retrieval Using DIN
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t22
Set-Up Time From DIN to Falling Edge of DCLK
5
ns
t23
Hold Time For DIN After Falling Edge of DCLK
4
ns
RETRIEVAL
BEFORE
CONV TOGGLES
(CONTINUOUS MODE)
Retrieval before CONV toggles is the most straightforward
method. Data retrieval begins soon after DVALID goes low
and finishes before CONV toggles; as shown in Figure 23.
For best performance, data retrieval must stop t
28
before
CONV toggles. This method is most appropriate for longer
integration times. The maximum time available for
readback is T
INT
– t
27
– t
28
. For DCLK = 10MHz and
CLK = 4MHz, the maximum number of DDC114s that can
be daisy-chained together with FORMAT = high is
calculated by Equation 1:
T
INT
355.125 s
80
DCLK
NOTE: 64
τ
DCLK
is for FORMAT = low.
Where
τ
DCLK
is the period of the data clock. For example,
if T
INT
= 1000
μ
s and DCLK = 10MHz, the maximum
number of DDC114s with FORMAT = high is shown in
Equation 2:
1000 s
355.125 s
(80)(100ns)
(or 100 for FORMAT = low)
80.60
80 DDC114s
RETRIEVAL
AFTER
CONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the
new data is ready. Data retrieval must wait t
29
after CONV
toggles before beginning. See Figure 24 for an example of
this. The maximum time available for retrieval is
t
27
t
29
– t
26
(344.875
μ
s – 10
μ
s – 1.75
μ
s for
CLK = 4MHz), regardless of T
INT
. The maximum number
of DDC114s that can be daisy-chained together with
FORMAT = high is calculated by Equation 3:
333.125 s
80
DCLK
NOTE: 64
τ
DCLK
is for FORMAT = low.
For DCLK = 10MHz, the maximum number of DDC114s is
41. (or 52 for FORMAT = low)
(1)
(2)
(3)
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| DDC114YK-7 | NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DDC114YK-7 | 制造商:Diodes Incorporated 功能描述:TRANS DGTL BJT NPN 100MA 6PIN SOT-26 - Tape and Reel |
| DDC114YK-7-F | 制造商:Diodes Incorporated 功能描述:PREBIASED TRANSISTOR SOT-26 R1<>R2 NPN 300MW 10KOHMS 47KOHMS - Tape and Reel |
| DDC114YU | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:NPN PRE-BIASED SMALL SIGNAL SOT-363 DUAL SURFACE MOUNT TRANSISTOR |
| DDC114YU-7 | 功能描述:開關晶體管 - 偏壓電阻器 DUAL NPN SOT-363 RoHS:否 制造商:ON Semiconductor 配置: 晶體管極性:NPN/PNP 典型輸入電阻器: 典型電阻器比率: 安裝風格:SMD/SMT 封裝 / 箱體: 直流集電極/Base Gain hfe Min:200 mA 最大工作頻率: 集電極—發(fā)射極最大電壓 VCEO:50 V 集電極連續(xù)電流:150 mA 峰值直流集電極電流: 功率耗散:200 mW 最大工作溫度: 封裝:Reel |
| DDC114YU-7-F | 功能描述:開關晶體管 - 偏壓電阻器 DUAL NPN SOT-363 RoHS:否 制造商:ON Semiconductor 配置: 晶體管極性:NPN/PNP 典型輸入電阻器: 典型電阻器比率: 安裝風格:SMD/SMT 封裝 / 箱體: 直流集電極/Base Gain hfe Min:200 mA 最大工作頻率: 集電極—發(fā)射極最大電壓 VCEO:50 V 集電極連續(xù)電流:150 mA 峰值直流集電極電流: 功率耗散:200 mW 最大工作溫度: 封裝:Reel |
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