參數(shù)資料
型號(hào)： DDC114EH-7
廠商： DIODES INC
元件分類： 功率晶體管
英文描述： NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
中文描述： 50 mA, 50 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR
封裝： GREEN, PLASTIC PACKAGE-6
文件頁(yè)數(shù)： 9/30頁(yè)
文件大?。?/td> 389K
代理商： DDC114EH-7
""#
SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
9
The digital interface of the DDC114 provides the digital
results via a synchronous serial interface consisting of
differential data clocks (DCLK and DCLK), a valid data pin
(DVALID), differential serial data output pins (DOUT and
DOUT), and differential serial data input pins (DIN and
DIN). The DDC114 contains only two A/D converters, so
the conversion process is interleaved (see Figure 2). The
integration and conversion process is fundamentally
independent of the data retrieval process. Consequently,
the CLK frequency and DCLK frequencies need not be the
same. DIN and DIN are only used when multiple
converters are cascaded and should be tied to DGND and
DVDD otherwise.
DEVICE OPERATION
Basic Integration Cycle
The topology of the front end of the DDC114 is a classical
analog integrator as shown in Figure 3. In this diagram,
only Input IN1 is shown. This representation of the input
stage consists of an operational amplifier, a selectable
feedback capacitor network (C
F
), and several switches
that implement the integration cycle. The timing
relationships of all of the switches shown in Figure 3 are
illustrated in Figure 4. Figure 4 is used to conceptualize
the operation of the integrator input stage of the DDC114
and should not be used as an exact timing tool for design.
See Figure 5 for the block diagrams of the reset, integrate,
converter, and wait states of the integrator section of the
DDC114. This internal switching network is controlled
externally with the convert command (CONV), range
selection pins (RANGE0-RANGE2), and the system clock
(CLK). For the best noise performance, CONV must be
synchronized with the rising edge of CLK. It is
recommended CONV toggle within
±
10ns of the rising
edge of CLK.
The noninverting inputs of the integrators are internally
referenced to ground. Consequently, the DDC114 analog
ground should be as clean as possible. The range
switches, along with the internal and external capacitors
(C
F
) are shown in parallel between the inverting input and
output of the operational amplifier. At the beginning of a
conversion, the switches S
A/D
, S
INTA
, S
INTB
, S
REF1
,
S
REF2
, and S
RESET
are set (see Figure 4).
50pF
25pF
12.5pF
VREF
RANGE2
RANGE1
RANGE0
To Converter
S
RESET
S
REF2
S
A/D1A
S
INTA
S
REF1
S
INTB
IN1
ESD
Protection
Diodes
Input
Current
Integrator A
Integrator B (same as A)
Photodiode
3pF
Figure 3. Basic Integration Configuration for Input 1, Shown with a 250pC (C
F
= 62.5pF) Input Range
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