參數(shù)資料
型號(hào): DDC112U/1K
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 2-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁(yè)數(shù): 1/34頁(yè)
文件大?。?/td> 776K
代理商: DDC112U/1K
DDC112
Dual Current Input 20-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q MONOLITHIC CHARGE MEASUREMENT A/D
CONVERTER
q DIGITAL FILTER NOISE REDUCTION:
3.2ppm, rms
q INTEGRAL LINEARITY:
±0.005% Reading ±0.5ppm FSR
q HIGH PRECISION, TRUE INTEGRATING FUNC-
TION
q PROGRAMMABLE FULL-SCALE
q SINGLE SUPPLY
q CASCADABLE OUTPUT
APPLICATIONS
q DIRECT PHOTOSENSOR DIGITIZATION
q CT SCANNER DAS
q INFRARED PYROMETER
q PRECISION PROCESS CONTROL
q LIQUID/GAS CHROMATOGRAPHY
q BLOOD ANALYSIS
DESCRIPTION
The DDC112 is a dual input, wide dynamic range, charge-
digitizing analog-to-digital (A/D) converter with 20-bit resolu-
tion. Low-level current output devices, such as photosensors,
can be directly connected to its inputs. Charge integration is
continuous as each input uses two integrators; while one is
being digitized, the other is integrating.
For each of its two inputs, the DDC112 combines current-to-
voltage conversion, continuous integration, programmable
full-scale range, A/D conversion, and digital filtering to achieve
a precision, wide dynamic range digital result. In addition to
the internal programmable full-scale ranges, external integrat-
ing capacitors allow an additional user-settable full-scale
range of up to 1000pC.
To provide single-supply operation, the internal A/D converter
utilizes a differential input, with the positive input tied to VREF.
When the integration capacitor is reset at the beginning of
each integration cycle, the capacitor charges to VREF. This
charge is removed in proportion to the input current. At the
end of the integration cycle, the remaining voltage is com-
pared to VREF.
The high-speed serial shift register which holds the result of
the last conversion can be configured to allow multiple DDC112
units to be cascaded, minimizing interconnections. The
DDC112 is available in an SO-28 or TQFP-32 package and is
offered in two performance grades.
Protected by US Patent #5841310
Dual
Switched
Integrator
Dual
Switched
Integrator
Σ
Modulator
Digital
Filter
Control
Digital
Input/Output
DVALID
DXMIT
DOUT
DIN
DCLK
RANGE2
RANGE1
RANGE0
TEST
CONV
CLK
CAP1A
CAP1B
CAP2A
CAP2B
IN2
IN1
VREF
DGND
DVDD
AGND
AVDD
CHANNEL 1
CHANNEL 2
SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004
DDC1
12
DDC
112
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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