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參數(shù)資料
| 型號(hào)： | DD00429VP-200 |
| 英文描述： | MIL-STD-1553/ARINC BUS CONTROLLER/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | DD00429VP-200 |
5
Data Device Corporation
www.ddc-web.com
DD-00429
IRQ Control Register 2. When programmed for pulse interrupt
mode, the associated interrupt pin will go low for 1 μS and return
high again. When programmed for LEVEL interrupt mode, the
interrupt will remain until the associated IRQ Status Register is
read, thus clearing the associated bits in each interrupt register.
Each of the individual interrupt registers can be masked by set-
ting their corresponding bit in IRQ Control Register 1. It should
be noted that the masking function only prevents the associated
IRQ pin from becoming active. When the mask bit is cleared, an
interrupt can occur in LEVEL IRQ mode if one or more interrupt
conditions occurred during the time when the mask was set. If
the user needs to ensure the interrupt will not occur upon clear-
ing the mask bit, the CPU should be programmed to read the
associated interrupt status register immediately prior to clearing
the IRQ mask bit.
Zero Wait Mode Operation:
When Zero Wait Mode is enabled
by not grounding the ZERO WAIT pin, the host microprocessor
may read data from the DD-00429 shared memory resources
(DMT and Rx RAM) without using the READY or DTACK signals
to insert wait states into the microprocessor cycle. This is
accomplished by an additional “dummy read” of the desired
address. This dummy read causes the DD-00429 to fetch the
data from the source and place it in a latch. The data can then
be read from the latch (word-by-word or byte-by-byte) by read-
ing the same addresses.Thus for a 32-bit read in 8-bit mode, the
microprocessor would perform a total of five read operations.
The first read would be the dummy read; subsequent reads
would transfer the data.
40
GND
80
GND
120
TABLE 4. DD-00429FP (160-PIN PQFP) ASIC PINOUTS
DESCRIPTION
GND
160
GND
39
+5V
79
BIST TOB (N/C)
119
BIST R2 (N/C)
159
TX DB10
PIN NO.
DESCRIPTION
+5V
TX DB11
TX DB12
TX DB13
TX DB14
TX DB15
EN RX1
EN RX0
SELECT
RX RDY1
RX RDY0
GND
GND
GND
INT/ MOTO
8/16
+5V
TX0 A
TX0 B
TX1 A
TX1 B
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CS0
CS1
CS2
BIST R3 (N/C)
GND
PIN NO.
PIN NO.
DESCRIPTION
PIN NO.
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
+5V
XTAL1 (N/C)
GND
TSB2 (N/C)
TSB3 (N/C)
TSA0 (N/C)
TSA1 (N/C)
TSA2 (N/C)
TSA3 (N/C)
TMA0 (N/C)
TMA1 (N/C)
TMA2 (N/C)
TMA3 (N/C)
TMA4 (N/C)
TMA5 (N/C)
TMA6 (N/C)
TMA7 (N/C)
TSB0 (N/C)
TSB1 (N/C)
+5V
GND
TMB0 (N/C)
TMB1 (N/C)
TMB2 (N/C)
TMB3 (N/C)
TMB4 (N/C)
TMB5 (N/C)
TMB6 (N/C)
TMB7 (N/C)
ZERO WAIT MODE
READY
RD or DS
WR or RD/ WR
DTACK
ERROR
MASTER RESET
+5V
BIST TOA (N/C)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
+5V
OSC CLK OUT (N/C)
BIST T1A (N/C)
BIST T1B (N/C)
BIST DMT (N/C)
BIST RAM7 (N/C)
BIST RAM24 (N/C)
D0
D1
D2
D3
D4
D5
D6
D7
GND
+5V
GND
+5V
D8
D9
D10
D11
D12
D13
D14
D15
GND
GND
IRQ3
IRQ2
IRQ1
RESET RC
ARINC CLK OUT
ARINC CLK 1
ARINC CLK 0
BIST R0 (N/C)
BIST R1 (N/C)
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
+5V
RESET 1
CW STRB1
EN TX1 OUT
TX1 B IN
TX1 A IN
TX1 EMPTY
LD TX1 HI
LD TX1 LOW
+5V
GND
+5V
16 MHZ CLOCK
EN RX3
EN RX2
RX RDY 3
RX RDY 2
+5V
GND
RESET 0
CW STRB0
EN TX0 OUT
TX0B IN
TX0A IN
TX0 EMPTY
LOAD TX0 HI
LD TX0 LOW
GND
TX DB0
TX DB1
TX DB2
TX DB3
TX DB4
TX DB5
TX DB6
TX DB7
TX DB8
TX DB9
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