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參數(shù)資料
| 型號： | DD-03182DC-100 |
| 英文描述： | Line Driver |
| 中文描述： | 線路驅(qū)動器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 221K |
| 代理商： | DD-03182DC-100 |
5
TABLE 5. DD-03182 PINOUTS
PIN NUMBER
DC OR GP
PACKAGE
V
REF
PP PACKAGE
V
REF
PP PACKAGE
DC OR GP
PACKAGE
PIN NUMBER
VP PACKAGE
V
REF
1
GND
N/C
15
2
N/C
N/C
+V
V
1
16
N/C
3
SYNC
GND
B
OUT
17
SYNC
4
DATA (A)
SYNC
N/C
18
DATA (A)
5
C
A
N/C
N/C
19
C
A
6
A
OUT
DATA (A)
N/C
20
A
OUT
7
-V
N/C
N/C
21
-V
8
GND
N/C
C
B
22
GND
9
+V
C
A
DATA (B)
23
+V
10
N/C
N/C
N/C
24
B
OUT
11
B
OUT
N/C
CLOCK
25
C
B
12
C
B
N/C
N/C
26
DATA (B)
13
DATA (B)
A
OUT
N/C
27
CLOCK
14
CLOCK
-V
V
1
28
V
1
SLEW RATE VS.TIMING CAPACITOR VALUES
The output slew rates are controlled by timing capacitors C
A
and
C
B
, and are charged by ±200 μA (nominal).Slew rate (SR) is cal-
culated by:
SR = 200/C (V/μsec), where C is in pF (equation 1).
HIGH-SPEED SLEW RATE
C
A
and C
B
= 75 pF for 100 kbps
From equation 1: 200/75 = 2.67 V/μsec
10% - 90% = 0.5 V to 4.5 V
= 4.0 V
For 100 kbps bit rate, the slew rate specification is 1.5 μsec
±0.5 μsec. Slew rate range (1.0 to 2.0 μsec).
200/SR = Capacitor, in pF
200/2.67 = 75 pF
(2.67 V/μsec)(1.5) = 4.0 V
SR = 4/(Rise Time)
4 μsec = 4V/1 μsec
Capacitor = 200/4 = 50 pF
2 μsec = 4V/2 μsec
Capacitor = 200/2 = 100 pF
LOW-SPEED SLEW RATE
C
A
and C
B
= 500 pF for 12.5 kbps
From equation 1: 200/500 = 0.4 V/μsec
For 12.5 kbps bit rate, the slew rate specification is 10 μsec
±5.0 μsec. Slew rate range (5 to 15 μsec).
200/SR = Capacitor in pF
200/0.4 = 500 pF
(0.4 V/μsec)(10) = 4.0 V
SR = 4/(Rise Time)
0.8 μsec = 4V/5 μsec
Capacitor = 200/0.8 = 250 pF
0.267 μsec = 4V/15 μsec Capacitor = 200/0.267 = 750 pF
DD-03182 PIN FUNCTIONS
Refer to FIGURES 7, 8 and 9 and TABLE 5 for specific package
pin configurations.
V
REF
(Input) – the voltage on V
REF
sets the output voltage levels
on A
OUT
and B
OUT
.
The output logic level swings between
+V
REF
REF
volts.
N/C – No Connection
SYNC (Input) – Logic 0 outputs will be forced to NULL or MARK
state. Logic 1 enables data transmission.
CLOCK (Input) – Logic 0 outputs will be forced to NULL or
MARK state. Logic 1 enables data transmission.
DATA(A)/DATA(B) (Inputs) – These signals contain the serial
data to be transmitted on the ARINC 429 data bus.
C
A
/C
B
(Analog) – External timing capacitors are tied from these
points to ground to establish the output signal slew rate.
Typically, C
=C
B
=75 pF for 100 kHz data and C
A
=C
B
=500 pF for
12.5 kHz data.
A
/B
(Output) – These are the line driver outputs which
are connected to the aircraft serial data bus.
-V (Input) – This is the negative supply input (-15 VDC nominal).
GND – Ground
+V (Input) – This is the positive supply input (+15 VDC nominal).
V
1
(Input) – This is the logic supply input (+5 VDC nominal).
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| DD-03182GP-200T | Line Driver |
| DD-03182GP-220 | Line Driver |
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| DD03182GP30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| DD03182PP20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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