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參數(shù)資料
| 型號(hào)： | DD-00429VP-200 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 301K |
| 代理商： | DD-00429VP-200 |
5
Data Device Corporation
www.ddc-web.com
DD-00429
G1 web-09/02-0
PROCESSOR INTERFACE
The processor interface allows for the use of either an 8- or 16-
bit data bus. Intel or Motorola control signal formats can also be
used.
INTERRUPT OPERATIONAL MODES
The DD-00429 provides four interrupt outputs. Three of these
interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose
programmable interrupts.The fourth interrupt is an Error interrupt
output which is specifically used to provide indications of various
error conditions and is nonmaskable.
ERROR INTERRUPT OPERATION
When an error condition occurs, the ERROR output pin goes low
to indicate the presence of an error. The error pin will go high
again when the Error Status Register is clear. Each of these bits
is cleared by either reading the Error Status Register or remov-
ing the error condition.
GENERAL PURPOSE INTERRUPTS
The three general purpose interrupt outputs can be used for mul-
tilevel interrupts or to trigger other external hardware for various
conditions. Each condition can be mapped to any one of the
three general purpose interrupts or disabled (by mapping to
IRQ0 which does not exist). Each interrupt output can be pro-
grammed to be either a LEVEL interrupt or PULSE interrupt via
the associated IRQ Control Register 2. When programmed for
pulse interrupt mode, the associated interrupt pin will go low for
1 μS and return high again. When programmed for LEVEL inter-
rupt mode, the interrupt will remain until the associated IRQ
Status Register is read, thus clearing the associated bits in each
interrupt register.
Each of the individual interrupt registers can be masked by set-
ting their corresponding bit in IRQ Control Register 1. It should
be noted that the masking function only prevents the associated
IRQ pin from becoming active. When the mask bit is cleared, an
interrupt can occur in LEVEL IRQ mode if one or more interrupt
conditions occurred during the time when the mask was set. If
the user needs to ensure the interrupt will not occur upon clear-
ing the mask bit, the CPU should be programmed to read the
associated interrupt status register immediately prior to clearing
the IRQ mask bit.
ZERO WAIT MODE OPERATION
When Zero Wait Mode is enabled by not grounding the ZERO
WAIT pin, the host microprocessor may read data from the DD-
00429 shared memory resources (DMT and Rx RAM) without
using the READY or DTACK signals to insert wait states into the
microprocessor cycle. This is accomplished by an additional
“
dummy read
”
of the desired address. This dummy read causes
the DD-00429 to fetch the data from the source and place it in a
latch.The data can then be read from the latch (word-by-word or
byte-by-byte) by reading the same addresses. Thus for a 32-bit
read in 8-bit mode, the microprocessor would perform a total of
five read operations. The first read would be the dummy read;
subsequent reads would transfer the data.
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