參數(shù)資料
型號: DD-00429FP-200
英文描述: MIL-STD-1553/ARINC Bus Controller/RTU
中文描述: MIL-STD-1553/ARINC總線控制器/ RTU通訊
文件頁數(shù): 3/8頁
文件大小: 301K
代理商: DD-00429FP-200
3
Data Device Corporation
www.ddc-web.com
DD-00429
G1 web-09/02-0
TABLE 1. DD-00429 ABSOLUTE MAXIMUM RATINGS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
PARAMETER
MIN
MAX
UNITS
DC Supply Voltage
Signal Input Voltage (logic inputs)
Storage Temperature
Operating Temperature
Lead Temperature (soldering)
Body Temperature (soldering)
7.0
Vdc
Vdc
°
C
°
C
°
C
°
C
-0.3
-0.3
-85
-40
Vdd+0.3
125
85
280 (for 3 sec)
210 (for 30 sec)
SYMBOL
MIN
MAX
UNITS
COMMENTS
PARAMETER
Iil
Schmitt
0
Threshold
Vt-
Vdc
0.2*Vdd
All other Inputs. (See Note 1).
μA
1.0
-1.0
Input Logic Current Low
Vdd
Input Logic Current Low
Idd
Input pins with internal pull-up logic: INT/MOT*,
8/16*, ZERO WAIT MODE and MASTER
RESET* @ Vdd = 5.5V
μA
-137
-25.3
Schmitt
1
Threshold
Vdc
Vt+
Iil
Vdc
0.8*Vdd
DC Supply Current
Device operation @ 16 MHz,
Typical Idd = 38.4 mA @ 5.0V. (@85
°
C)
mA
42.2
5.5
4.5
DC Supply Voltage
LOGIC INPUTS/OUTPUTS
TABLE 2. DD-00429 SPECIFICATIONS (TC = +25°C UNLESS OTHERWISE SPECIFIED)
RESET RC*, 16 MHZ CLOCK
RESET RC*, 16 MHZ CLOCK
Vil
All other Inputs. (See Note 1).
Vdc
0.8
Input Logic Voltage Low
Schmitt Hysteresis
RESET RC*, 16 MHZ CLOCK
Vdc
1
Vh
Input Logic Voltage High
All other Inputs. (See Note 1).
Vdc
2.0
Vih
Iih
All other Inputs. (See Note 1).
μA
1.0
-1.0
Input Logic Current High
Vol
Io1=3.84 mA minimum @Vdd= 4.5V.
(See note 2)
Vdc
0.4
Output Voltage Logic Low
Voh
Ioh=3.84 mA minimum @Vdd= 4.5V.
(See note 2)
Vdc
2.4
Output Voltage Logic High
Ioz
For TXDB0-TXDB15, D0-D15, READY,
DTACK*, ERROR*, IRQ3*, IRQ2* and IRQ1 @
vdd = 5.5V
μA
10
-10
Output Leakage Current, Hi-Z
NOTES:
1.TTL compatible input logic voltage levels at CMOS input logic current levels.
2. CMOS output logic voltage at current levels.
ARINC 429 RECEIVERS
The DD-00429 supports four ARINC 429 inputs, designated
Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The
architecture of each of the four receiver circuits is identical and
each receives data independently. ARINC 429 data is directly
received into the ARINC 429 transceiver. Input protection, in
accordance with the ARINC 429 specification, is provided along
with voltage level translation from +5 V bipolar, nonreturn-to-zero
data to conventional, +5 V logic levels.
Receive Data Rates:
Data rates can be programmed for chan-
nels 0 and 1 independently of channels 2 and 3 via bits 2 and 3
of Arinc Control Register 2. The receiver circuitry will success-
fully decode an incoming ARINC 429 data stream as long as the
data rate is within ±5% of the nominal rate as determined by the
Hi Speed/Low Speed Bit and the associated ARINC Clock input
(ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock
inputs may be tied to the 1 MHz clock output or may be con-
nected to another clock source.
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