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參數(shù)資料
| 型號： | DC74HC259 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | FPGA, 12K LUTS, 93 I/O,DSP,144TQFP; Logic IC family:ECP2; Logic IC function:FPGA; Voltage, supply:1.2V; Case style:TQFP; Base number:2; I/O lines, No. of:93; Logic function number:LFE2-12E; Pins, No. of:144; Temp, op. max:85(degree RoHS Compliant: Yes |
| 中文描述： | 高速CMOS邏輯8位可尋址鎖存器 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 62K |
| 代理商： | DC74HC259 |
8
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE:
V
CC
, C
L
= 50pF.
Open drain waveforms t
PLZ
and t
PZL
are the same as those for three-state shown on the left. The test circuit is Output R
L
= 1k
to
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
50%
10%
90%
GND
V
CC
10%
90%
50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
6ns
6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
0.3
2.7
GND
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
t
r
6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
6ns
t
f
1.3
IC WITH
THREE-
STATE
OUTPUT
OUTPUT
R
L
= 1k
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
V
CC
FOR t
PLZ
AND t
PZL
GND FOR t
PHZ
AND t
PZH
C
L
50pF
CD74HC259, CD74HCT259
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