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參數(shù)資料
| 型號(hào)： | DC1562A-H |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL LTC6993-2 |
| 設(shè)計(jì)資源： | DC1562A Design Files DC1562A Schematic |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TimerBlox® |
| 主要目的： | 定時(shí)，單穩(wěn)多諧振蕩器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC6993-2 |
| 主要屬性： | 上升沿觸發(fā)器，可再觸發(fā) |
| 次要屬性： | 2.25 V ~ 5.5 V 電源 |
| 已供物品： | 板 |
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
15
69931234fb
OPERATION
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6993 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE = 16 (DIVCODE + 6) tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. How-
ever, if the output pulse is active during the transition, the
pulse width can take on a value between the two settings.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART. The OUT pin
is held low during this time. The typical value for tSTART
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of NDIV):
tSTART(TYP) = 500 tMASTER
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before an output pulse can be
generated. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
pin so it will properly track V+. Less than 100pF will not
extend the start-up time.
TheDIVCODEsettingisrecognizedattheendofthestartup
up. If POL = 1, the output will transition high. Otherwise
(if POL = 0) OUT simply remains low. At this point, the
LTC6993 is ready to respond to rising/falling edges on
the TRIG input.
Figure 5a. DIVCODE Change from 0 to 2
Figure 5b. DIVCODE Change from 2 to 0
Figure 6. Start-Up Timing Diagram
DIV
500mV/DIV
TRIG
2V/DIV
OUT
2V/DIV
LTC6993-1
V+ = 3.3V
RSET = 200k
200s/DIV
69931234 F05a
512s
256s
4s
DIV
500mV/DIV
TRIG
2V/DIV
OUT
2V/DIV
LTC6993-1
V+ = 3.3V
RSET = 200k
200s/DIV
69931234 F05b
512s
256s
4s
TRIG
V+
OUT
tSTART
(TRIG IGNORED)
tOUT
POL = 1
69931234 F06
POL = 0
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參數(shù)描述 |
|---|---|
| DC1562A-I | 功能描述:BOARD EVAL LTC6993-3 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:數(shù)字電位器 嵌入式:- 已用 IC / 零件:AD5258 主要屬性:- 次要屬性:- 已供物品:板 相關(guān)產(chǎn)品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
| DC1562A-J | 功能描述:BOARD EVAL LTC6993-4 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| DC1562A-K | 功能描述:BOARD EVAL LTC6994-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| DC1562A-L | 功能描述:BOARD EVAL LTC6994-2 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| DC1562B-B | 制造商:Linear Technology 功能描述:LTC6991 DEMO BOARD 1Hz (1s) Fixed Frequenc |
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