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參數資料
| 型號： | DC1444A-A |
| 廠商： | Linear Technology |
| 文件頁數： | 13/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC2301 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC1444A Design File DC1444A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數量： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 14k |
| 數據接口： | I²C，串行 |
| 在以下條件下的電源（標準）： | 1.5mW @ 1kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2301 |
| 已供物品： | 板 |
| 相關產品： | LTC2301IMS#TRPBF-ND - IC ADC 12-BIT 1CHN 12-MSOP LTC2301IDE#TRPBF-ND - IC ADC 12-BIT 1CHN 12-DFN LTC2301IDE#PBF-ND - IC ADC 12-BIT 1CHN 12-DFN LTC2301HMS#TRPBF-ND - IC ADC 12-BIT 1CHN 12-MSOP LTC2301HMS#PBF-ND - IC ADC 12-BIT 1CHN 12-MSOP LTC2301CMS#TRPBF-ND - IC ADC 12-BIT 1CHN 12-MSOP LTC2301CMS#PBF-ND - IC ADC 12-BIT 1CHN 12-MSOP LTC2301CDE#TRPBF-ND - IC ADC 12-BIT 1CHN 12-DFN LTC2301IMS#PBF-ND - IC ADC 12BIT I2C 12-MSOP LTC2301CDE#PBF-ND - IC ADC 12BIT I2C 12-DFN |
LTC2301/LTC2305
20
23015fb
APPLICATIONS INFORMATION
Sleep Mode
The ADCs enter sleep mode after a conversion is complete
(tCONV) if the SLP bit is set to a logic 1. The ADCs draw
only 7μA in sleep mode, provided that none of the digital
inputs are switching. When the LTC2301/LTC2305 are
properly addressed, the ADCs are released from sleep
mode and require 200ms (tREFWAKE) to wake up and charge
the respective 2.2μF and 10μF bypass capacitors on the
VREF and REFCOMP pins. A new conversion should not be
initiated before this time, as shown in Figure 11.
Acquisition
The LTC2301/LTC2305 begin acquiring the input signal at
different instances depending on whether a read or write
operation is being performed. If a read operation is being
performed, acquisition of the input signal begins on the
rising edge of the 9th clock pulse following the address
frame, as shown in Figure 12a.
If a write operation is being performed, acquisition of the
input signal begins on the falling edge of the sixth clock
cycle after the DIN word has been shifted in, as shown in
Figure 12b. The LTC2301/LTC2305 will acquire the signal
from the input channel that was most recently programmed
by the DIN word. A minimum of 240ns is required to acquire
the input signal before initiating a new conversion.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
board should ensure digital and analog signal lines are
S
CONVERSION
SLEEP
tREFWAKE
CONVERSION
R/W
ACK
7-BIT ADDRESS
P
23015 F11
Figure 11. Exiting Sleep Mode and Starting a New Conversion
Figure 12a. Timing Diagram Showing Acquisition During a Read Operation
12
A6
SDA
SCL
A5
A4
A3
A2
A1
A0
R/W
3456789
12
B11
ACQUISITION BEGINS
tACQ
23015 F12a
B10
Figure 12b. Timing Diagram Showing Acquisition During a Write Operation
12
A2
A1
A0
R/W
SDA
SCL
S/D
O/S
X
UNI
X
345
56789
6789
ACQUISITION BEGINS
tACQ
23015 F12b
SLP
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