For more information www.linear.com/LTC2258-14
參數(shù)資料
型號(hào)： DC1370A-F
廠商： Linear Technology
文件頁數(shù)： 31/34頁
文件大?。?/td> 0K
描述： BOARD DEMO 25MSPS LTC2256-14
軟件下載： QuikEval II System
設(shè)計(jì)資源： DC1370A Design Files
標(biāo)準(zhǔn)包裝： 1
系列： *
相關(guān)產(chǎn)品： DC718C-ND - DEMO QUIKEVAL-II DATA
LTC2258-14
LTC2257-14/LTC2256-14
6
225814fc
For more information www.linear.com/LTC2258-14
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTC2258-14
LTC2257-14
LTC2256-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.1
1.9
1.1
1.9
1.1
1.9
V
IVDD
Analog Supply Current
DC Input
Sine Wave Input
l
44.7
45.3
49.5
27
27.9
30
19.5
19.9
22
mA
IOVDD
Digital Supply Current
Sine Wave Input, OVDD=1.2V
2.6
1.6
1.1
mA
PDISS
Power Dissipation
DC Input
Sine Wave Input, OVDD=1.2V
l
80.5
84.7
90
48.6
52.1
54
35.1
37.1
40
mW
LVDS Output Mode
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.9
1.7
1.9
1.7
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
48.9
54
31.4
35
23.5
26
mA
IOVDD
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
20.7
40.5
23
44
20.7
40.5
23
44
20.7
40.5
23
44
mA
PDISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
125.3
160.9
139
177
93.8
129.4
105
143
79.6
115.2
89
126
mW
All Output Modes
PSLEEP
Sleep Mode Power
0.5
mW
PNAP
Nap Mode Power
9
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10
mW
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTC2258-14
LTC2257-14
LTC2256-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Note 10)
l
1
65
1
40
1
25
MHz
tL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
7.3
2.0
7.69
500
11.88
2.00
12.5
500
19
2.00
20
500
ns
tH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
7.3
2.0
7.69
500
11.88
2.00
12.5
500
19
2.00
20
500
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
5.0
5.5
Cycles
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