For more information www.linear.com/LTC2258-14 applicaTion" />
參數(shù)資料
型號(hào)： DC1370A-D
廠商： Linear Technology
文件頁(yè)數(shù)： 14/34頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO 65MSPS LTC2258-14
軟件下載： QuikEval II System
設(shè)計(jì)資源： DC1370A Design Files
標(biāo)準(zhǔn)包裝： 1
系列： *
相關(guān)產(chǎn)品： DC718C-ND - DEMO QUIKEVAL-II DATA
21
225814fc
LTC2258-14
LTC2257-14/LTC2256-14
For more information www.linear.com/LTC2258-14
applicaTions inForMaTion
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinu-
soidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC– should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For good
jitter performance ENC+ and ENC– should have fast rise
and fall times.
Thesingle-endedencodemodeshouldbeusedwithCMOS
encode inputs. To select this mode, ENC– is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to3.3VCMOSlogiclevelscanbeused.TheENC+threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
VDD
LTC2258-14
225814 F10
ENC–
ENC+
15k
VDD
DIFFERENTIAL
COMPARATOR
30k
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
30k
ENC+
ENC–
225814 F11
0V
1.8V TO 3.3V
LTC2258-14
CMOS LOGIC
BUFFER
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
100
25
D1
ENC+
ENC–
0.1F
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
225814 F12
LTC2258-14
T1
1:4
Figure 12. Sinusoidal Encode Drive
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1F
225814 F13
LTC2258-14
Figure 13. PECL or LVDS Encode Drive
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