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參數(shù)資料
| 型號： | DC1012A-B |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2497 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC1012A Schematic DC1012A Design File |
| 標準包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 已用 IC / 零件： | LTC2497 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | LTC2497CUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2497IUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2497IUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2497CUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN |
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LTC2497
2497fa
I2C INTERFACE
The LTC2497 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and multiple masters on a single bus. The
connected devices can only pull the data line (SDA) low
and can never drive it high. SDA is required to be externally
connected to the supply through a pull-up resistor. When
the data line is not being driven, it is high. Data on the
I2C bus can be transferred at rates up to 100kbits/s in the
standard mode and up to 400kbits/s in the fast mode.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
canalsobeconsideredasmastersorslaveswhenperform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.
The LTC2497 can only be addressed as a slave. Once ad-
dressed, it can receive channel selection bits or transmit
the last conversion result. The serial clock line, SCL, is
always an input to the LTC2497 and the serial data line SDA
isbidirectional.Thedevicesupportsthestandardmodeand
the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I2C timing.
The Start and Stop Conditions
AStart(S)conditionisgeneratedbytransitioningSDAfrom
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is
finished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is high. The bus is free
after a Stop is generated. Start and Stop conditions are
always generated by the master.
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the Start condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.
DATA FORMAT
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for a
read request and 0 for a write request. If the 7-bit address
matches the hard wired, LTC2497’s address (one of 27
pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2497 issues an ACK by pulling the SDA line low.
SDA
SCL
S
Sr
P
S
tHD(SDA)
tHD(DAT)
tSU(STA)
tSU(STO)
tSU(DAT)
tLOW
tHD(SDA)
tSP
tBUF
tr
tf
tr
tf
tHIGH
2497 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
applicaTions inForMaTion
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