參數(shù)資料
型號(hào)： DAC908
英文描述： 8-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER
中文描述： 8位，165MSPS的速率，數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 2/15頁(yè)
文件大?。?/td> 180K
代理商： DAC908
DAC908
2
SPECIFICATIONS
At T
A
= full specified temperature range, +V
A
= +5V, +V
D
= +5V, differential transformer coupled output, 50
doubly terminated, unless otherwise specified.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC908U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
Output Update Rate (f
CLOCK
)
Output Update Rate
Full Specified Temperature Range, Operating
8
Bits
MSPS
MSPS
°
C
4.5V to 5.5V
2.7V to 3.3V
Ambient, T
A
T
= +25
°
C
165
125
–40
200
165
+85
STATIC ACCURACY
(1)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
f
CLOCK
= 25MSPS, f
OUT
= 1.0MHz
–0.5
–0.5
±
0.25
±
0.25
+0.5
+0.5
LSB
LSB
DYNAMIC PERFORMANCE
Spurious Free Dynamic Range (SFDR)
f
OUT
= 1.0MHz, f
CLOCK
= 25MSPS
f
OUT
= 2.1MHz, f
CLOCK
= 50MSPS
f
OUT
= 5.04MHz, f
CLOCK
= 50MSPS
f
OUT
= 5.04MHz, f
CLOCK
= 100MSPS
f
OUT
= 20.2MHz, f
CLOCK
= 100MSPS
f
OUT
= 25.3MHz, f
CLOCK
= 125MSPS
f
OUT
= 41.5MHz, f
CLOCK
= 125MSPS
f
OUT
= 27.4MHz, f
CLOCK
= 165MSPS
f
OUT
= 54.8MHz, f
CLOCK
= 165MSPS
Spurious Free Dynamic Range within a Window
f
OUT
= 2.1MHz, f
CLOCK
= 50MSPS
f
= 5.04MHz, f
= 100MSPS
Total Harmonic Distortion (THD)
f
OUT
= 2.1MHz, f
CLOCK
= 50MSPS
f
OUT
= 5.04MHz, f
CLOCK
= 100MSPS
f
= 20.2MHz, f
C(2)
= 100MSPS
Output Settling Time
Output Rise Time
(2)
Output Fall Time
(2)
Glitch Impulse
T
A
= +25
°
C
To Nyquist
64
70
69
67
67
61
57
51
58
52
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
2MHz Span
4MHz Span
70
69
dBc
dBc
–72
–66
–60
30
2
2
3
dBc
dBc
dBc
ns
ns
ns
pV-s
to 0.1%
10% to 90%
10% to 90%
DC-ACCURACY
Full-Scale Output Range
(3)
(FSR)
Output Compliance Range
Gain Error
Gain Error
Gain Drift
Offset Error
Offset Drift
Power Supply Rejection, +V
A
Power Supply Rejection, +V
D
Output Noise
Output Resistance
Output Capacitance
All Bits High, I
OUT
2.0
–1.0
–10
–10
20.0
+1.25
+10
+10
mA
V
%FSR
%FSR
ppmFSR/
°
C
%FSR
ppmFSR/
°
C
%FSR/V
%FSR/V
pA/
√
Hz
k
pF
With Internal Reference
With External Reference
With Internal Reference
With Internal Reference
With Internal Reference
±
1
±
2
±
120
–0.025
+0.025
±
0.1
–0.2
–0.025
+0.2
+0.025
I
OUT
= 20mA, R
LOAD
= 50
50
200
12
I
OUT
, I
OUT
to Ground
REFERENCE
Reference Voltage
Reference Tolerance
Reference Voltage Drift
Reference Output Current
Reference Input Resistance
Reference Input Compliance Range
Reference Small Signal Bandwidth
(4)
+1.24
±
5
±
50
10
1
V
%
ppmFSR/
°
C
μ
A
M
V
MHz
0.1
1.25
1.3
DIGITAL INPUTS
Logic Coding
Latch Command
Logic High Voltage, V
IH
Logic Low Voltage, V
IL
Logic High Voltage, V
IH
Logic Low Voltage, V
Logic High Current
,
I
IIL
Logic Low Current, I
IL
Input Capacitance
Straight Binary
Rising Edge of Clock
5
0
3
0
±
20
±
20
5
+V
D
= +5V
+V
D
= +5V
+V
D
= +3V
+V
D
= +3V
+V
D
= +5V
+V
D
= +5V
3.5
V
V
V
V
μ
A
μ
A
pF
1.2
2
0.8
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