參數(shù)資料
型號(hào): DAC8814ICDB
廠商: Texas Instruments, Inc.
英文描述: Quad, Serial Input 16-Bit Multiplying Digital-to-Analog Converter
中文描述: 四,串行輸入16位乘法數(shù)字到模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 26/31頁(yè)
文件大?。?/td> 264K
代理商: DAC8814ICDB
www.ti.com
P
A
B
C
D
Address
Decoder
Shift Register
EN
To Input Register
CS
CLK
SDI
SDO
19
th
/17
th
CLOCK
POWER ON RESET
When the V
DD
power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the
zero-code state or half-scale, depending on the MSB pin voltage. The V
DD
power supply should have a smooth
positive ramp without drooping in order to have consistent results, especially in the region of V
DD
= 1.5 V to
2.3 V. The V
SS
supply has no effect on the power-on reset performance. The DAC register data stays at zero or
half-scale setting until a valid serial register data load takes place.
ESD Protection Circuits
V
DD
5 k
DGND
DIGITAL
INPUTS
DAC8814
SBAS338–JANUARY 2005
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8814,
Table 1, Table 2, Table 3 and Figure 53 define the characteristics of the software serial interface. Figure 57
shows the equivalent logic interface for the key digital control pins for the DAC8814.
Figure 57. DAC8814 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and V
DD
as
shown in Figure 58.
Figure 58. Equivalent ESD Protection Circuits
26
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