VDD DATA DAC-8562 13 10F 0.1F –5V
參數(shù)資料
型號: DAC8562FS
廠商: Analog Devices Inc
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT PARALLEL 5V 20-SOIC
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 37
設置時間: 16µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 30mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC W
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 62.5k
DAC8562
REV. A
–11–
15
16
DGND
AGND
VDD
DATA
DAC-8562
13
10F
0.1F
–5V
V
O +5V
+5V
10
CE
CLR
20
12
14
REFOUT
VOUT
R1
10k
R2
12.7k
–2.5V
2
3
4
8
A1
+5V
–5V
1
P2
500
FULL SCALE
ADJUST
R4
23.7k
P1
10k
ZERO SCALE
ADJUST
R3
247k
R5
10k
R6
10k
6
5
A2
7
A1, A2 = 1/2 OP-295
Figure 33. Bipolar Output Operation
Bipolar Output Operation
Although the DAC8562 has been designed for single supply op-
eration, bipolar operation is achievable using the circuit illus-
trated in Figure 33. The circuit uses a single supply, rail-to-rail
OP295 op amp and the DAC’s internal +2.5 V reference to gen-
erate the –2.5 V reference required to level-shift the DAC out-
put voltage. The circuit has been configured to provide an
output voltage in the range –5 V
≤ V
OUT
≤ +5 V and is coded in
complementary offset binary. Although each DAC LSB corre-
sponds to 1 mV, each output LSB has been scaled to 2.44 mV.
Table IV provides the relationship between the digital codes and
output voltage.
The transfer function of the circuit is given by:
V
O =1 mV × Digital Code ×
R4
R1
+ 2.5 × R4
R2
and, for the circuit values shown, becomes:
V
O = –2. 44 mV × Digital Code + 5 V
Table IV. Bipolar Code Table
Hexadecimal Number
Decimal Number
Analog Output
in DAC Register
Voltage (V)
FFF
4095
–4 9976
801
2049
–2.44E–3
800
2048
0
7FF
2047
+2.44E–3
000
0
+5
To maintain monotonicity and accuracy, R1, R2, R4, R5, and
R6 should be selected to match within 0.01% and must all be of
the same (preferably metal foil) type to assure temperature coef-
ficient matching. Mismatching between R1 and R2 causes offset
and gain errors while an R4 to R1 and R2 mismatch yields gain
errors.
For applications that do not require high accuracy, the circuit il-
lustrated in Figure 34 can also be used to generate a bipolar
output voltage. In this circuit, only one op amp is used and no
potentiometers are used for offset and gain trim The output
voltage is coded in offset binary and is given by:
V
O = 1 mV × Digital Code ×
R4
R3
+ R4
× 1+
R2
R1
– REFOUT
×
R2
R1
For the
±2 5 V output range and the circuit values shown in the
table, the transfer equation becomes:
V
O = 1.22 mV × Digital Code –2.5 V
Similarly, for the
±5 V output range, the transfer equation be-
comes:
V
O = 2. 44 mV × Digital Code –5 V
Note that, for
±5 V output voltage operation, R5 is required as a
pull-down for REFOUT. Or, REFOUT can be buffered by an
op amp configured as a follower that can source and sink cur-
rent.
15
16
DATA
DAC-8562
13
CE
CLR
DGND
AGND
10
12
VDD
0.1F
+5V
20
14
REFOUT
VOUT
R1
R5
4.99k
A1 = 1/2 OP-295
R4
R3
R2
2
3
4
8
A1
+5V
–5V
1
VO
VOUT
RANGE
±2.5V
±5V
R1
10k
R2
10k
20k
R3
10k
R4
15.4k + 274
43.2k + 499
Figure 34. Bipolar Output Operation Without
Trim Version 1
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