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參數資料
| 型號： | DAC8551IDRBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位，超低毛刺電壓輸出數字模擬轉換器 |
| 文件頁數： | 14/22頁 |
| 文件大?。?/td> | 1740K |
| 代理商： | DAC8551IDRBR |
www.ti.com
THEORY OF OPERATION
DAC SECTION
The architecture consists of a string DAC followed by
an output buffer amplifier.
Figure 47
shows a block
diagram of the DAC architecture.
62
V
FB
GND
VOUTX
DIN
65536
VREF
RESISTOR STRING
The resistor string section is shown in
Figure 48
. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
To Output
Amplifier
(2x Gain)
R
R
R
R
R
VREF
VREF
2
Divider
SERIAL INTERFACE
The DAC8551 has a 3-wire serial interface ( SYNC,
SCLK, and D
IN
), which is compatible with SPI,
QSPI, and Microwire interface standards, as well
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, which gives an
output range of 0 V to V
DD
. It is capable of driving a
load of 2 k
in parallel with 1000 pF to GND. The
source and sink capabilities of the output amplifier
can be seen in the typical curves. The slew rate is 1.8
V/μs with a full-scale setting time of 8 μs with the
output unloaded.
DAC8551
SLAS429A–APRIL 2005–REVISED JULY 2005
Figure 47. DAC8551 Architecture
The input coding to the DAC8551 is straight binary,
so the ideal output voltage is given by:
where D
IN
= decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535.
Figure 48. Resistor String
The write sequence begins by bringing the SYNC line
LOW. Data from the D
IN
line is clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 30 MHz, making
the DAC8551 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed (i.e., a change in DAC register contents
and/or a change in the mode of operation).
The inverting input of the output amplifier is brought
out to the V
FB
pin. This allows for better accuracy in
critical applications by tying the V
FB
point and the
amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected
between these points for specific applications.
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33 ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. As previously mentioned, it
must be brought HIGH again just before the next
write sequence.
14
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相關代理商/技術參數 |
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|---|---|
| DAC8551IDRBT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| DAC8552 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| DAC8552EVM | 功能描述:數據轉換 IC 開發(fā)工具 DAC CONVERTER RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| DAC8552IDGKR | 功能描述:數模轉換器- DAC 16-Bit Dual Channell DAC RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC8552IDGKRG4 | 功能描述:數模轉換器- DAC 16-Bit Dual Channell DAC RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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