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參數(shù)資料
| 型號： | DAC8512FSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 5V COMPLETE 8-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 98 |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
DAC8512
–15–
REV. A
A Digitally Controlled, Ultralow Noise VCA
The circuit in Figure 38 illustrates how the DAC8512 can be
used to control an ultralow noise VCA, using the AD600/
AD602. The AD600/AD602 is a dual, low noise, wideband,
variable gain amplifier based on the X-AMP topology.* Both
channels of the AD600 are wired in parallel to achieve a
wideband VCA which exhibits an RTI (Referred To Input)
noise voltage spectral density of approximately 1 nV/
√Hz. The
output of the VCA requires an AD844 configured in a gain of 4
to account for signal loss due to input and output 50
termina-
tions. As configured, the total gain in the circuit is 40 dB.
Since the output of the DAC8512 is single quadrant, it was nec-
essary to offset the AD600’s gain control voltage so that the gain
of the circuit is 0 dB for zero scale and 40 dB at full scale. This
was achieved by setting C1LO and C2LO to +625 mV using R1
and R2. Next, the output of the DAC8512 was scaled so that
the gain of the AD600 equaled 20 dB when the digital input
code equaled 800H. The frequency response of the VCA as a
function of digital code is shown in Figure 39.
*For more details regarding the AD600 or AD602, please consult the AD600/
AD602 data sheet.
+70
+20
–30
100k
100M
10M
1M
10k
+30
+40
+50
+60
–20
–10
0
+10
FREQUENCY – Hz
SYSTEM
GAIN
–
dB
4095
3072
2048
1024
0
Figure 39. VCA Frequency Response vs. Digital Code
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
AD600JN
V+
V–
0.1
F
0.1
F
6
2
DAC8512FZ
8
7
CS
CLR
1
0.1
F
V+
1
F
R6
2.26k
R7
1k
0
≤ V
G ≤ 1.25V
5
LD
3
SCLK
4
SDI
R1
619
R2
4.32k
V+
+625mV
6
3
2
0.1
F
0.1
F
V+
V
OUT
0.01dB/BIT
10
F
+5V
10
F
–5V
V+
V–
FB = FAIR RITE
#2743001111
SUPPLY DECOUPLING NETWORK
V–
R5
806
R3
402
R4
402
R4
49.9
V
IN
AD844
Figure 38. A Digitally Controlled, Ultralow Noise VCA
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