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參數(shù)資料
| 型號(hào)： | DAC8420ES-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD SRL LP 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 255mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 125k |
DAC8420
Rev. B | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
VOUTD 2
VOUTC 3
VREFLO 4
CLSEL
16
CLR
15
LD
14
NC
13
VREFHI 5
VOUTB 6
VOUTA 7
CS
12
CLK
11
SDI
10
VSS 8
GND
9
NC = NO CONNECT
DAC8420
TOP VIEW
(Not to Scale)
00
27
5-
0
04
Figure 4. PDIP and CERDIP
VDD 1
VOUTD 2
VOUTC 3
VREFLO 4
CLSEL
16
CLR
15
LD
14
NC
13
VREFHI 5
CS
12
VOUTB 6
CLK
11
VOUTA 7
SDI
10
VSS 8
GND
9
NC = NO CONNECT
DAC8420
TOP VIEW
(Not to Scale)
0
027
5-
00
5
Figure 5. SOIC
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply, 5 V to 15 V.
4
VREFLO
Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable
range is VSS to (VVREFHI 2.5 V).
5
VREFHI
Reference Input. Upper DAC ladder reference voltage input. Allowable range is (VDD 2.5 V) to
(VVREFLO + 2.5 V).
7, 6, 3, 2
VOUTA through VOUTD
Buffered DAC Analog Voltage Outputs.
8
VSS
Negative Power Supply, 0 V to 15 V.
9
GND
Power Supply, Digital Ground.
10
SDI
Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register,
which shifts data in, beginning with DAC Address Bit A1. This input is ignored when CS is high. SDI
is CMOS/TTL compatible. The format of the 16-bit serial word is shown in Table 8.
11
CLK
System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed
with CS.
12
CS
Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and
disables the serial data register input when high. When low, data input clocking is enabled (see
Table 6). CS is CMOS/TTL compatible.
13
NC
No Connect = Don’t Care.
14
LD
Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained
in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD,
independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible.
15
CLR
Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to
zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is
unaffected by this control. CLR is CMOS/TTL compatible.
16
CLSEL
Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A
through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS
/
TTL compatible.
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