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參數(shù)資料
| 型號： | DAC8408FT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Quad 8-Bit Multiplying CMOS D/A Converter with Memory |
| 中文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 0.19 us SETTLING TIME, 8-BIT DAC, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 217K |
| 代理商： | DAC8408FT |
DAC8408
–9–
REV. A
Figure 4. Equivalent DAC Circuit (AII Digital Inputs LOW)
DIGIT AL SE CT ION
Figure 5 shows the digital input/output structure for one bit.
T he digital WR,
WR
, and
RD
controls shown in the figure are
internally generated from the external A/
B
, R/
W
,
DS1
, and
DS2
signals. T he combination of these signals decide which DAC is
selected. T he digital inputs are CMOS inverters, designed such
that T T L input levels (2.4 V and 0.8 V) are converted into
CMOS logic levels. When the digital input is in the region of 1.2 V
to 1.8 V, the input stages operate in their linear region and draw
current from the +5 V supply (see T ypical Supply Current vs.
Logic Level curve on page 6). It is recommended that the digital
input voltages be as close to V
DD
and DGND as is practical in
order to minimize supply currents. T his allows maximum sav-
ings in power dissipation inherent with CMOS devices. T he
three-state readback digital output drivers (in the active mode)
provide T T L-compatible digital outputs with a fan-out of one
T T L load. T he three state digital readback leakage-current is
typically 5 nA.
Figure 5. Digital Input/Output Structure
INT E RFACE LOGIC SE CT ION
DAC Operating Modes
All DACs in HOLD MODE.
DAC A, B, C, or D individually selected (WRIT E MODE).
DAC A, B, C, or D individually selected (READ MODE).
DACs A and C simultaneously selected (WRIT E MODE).
DACs B and D simultaneously selected (WRIT E MODE).
DAC Selection:
Control inputs,
DS1
,
DS2
, and A/
B
select
which DAC can accept data from the input port (see Mode Se-
lection T able).
Mode Selection:
Control inputs
DS
and R/
W
control the oper-
ating mode of the selected DAC.
Write Mode:
When the control inputs
DS
and R/
W
are both
low, the selected DAC is in the write mode. T he input data
latches of the selected DAC are transparent, and its analog out-
put responds to activity on the data inputs DB0–DB7.
Hold Mode:
T he selected DAC latch retains the data that was
present on the bus line just prior to
DS
or R/
W
going to a high
state. All analog outputs remain at the values corresponding to
the data in their respective latches.
Read Mode:
When
DS
is low and R/
W
is high, the selected
DAC is in the read mode, and the data held in the appropriate
latch is put back onto the data bus.
MODE SE LE CT ION T ABLE
Control Logic
DS1
DS2
A/
B
R/
W
Mode
DAC
L
L
H
H
L
L
H
H
L
L
H
L
L
H
H
L
L
H
H
L
L
L
L
H
L
L
H
L
H
L
H
L
H
L
H
L
X
H
L
L
L
L
L
H
H
H
H
L
L
X
H
H
WRIT E
WRIT E
WRIT E
WRIT E
READ
READ
READ
READ
WRIT E
WRIT E
HOLD
HOLD
HOLD
A
B
C
D
A
B
C
D
A&C
B&D
A/B/C/D
A/B/C/D
A/B/C/D
L = Low State, H = High State, X = Irrelevant
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DAC8408G | 制造商:Analog Devices 功能描述: |
| DAC8408GBC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| DAC8408GP | 功能描述:IC DAC 8BIT QUAD W/MEMORY 28-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| DAC8408GPZ | 功能描述:IC DAC 8BIT QUAD W/MEMORY 28DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| DAC8408HP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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