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參數(shù)資料
| 型號： | DAC8248GP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 12-BIT DAC, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 350K |
| 代理商： | DAC8248GP |
DAC8248
–8–
REV. B
Four Cycle Update
Five Cycle Update
Write Timing Cycle Diagram
PARAME T E R DE FINIT IONS
RE SOLUT ION (N)
T he resolution of a DAC is the number of states (2
n
) that the
full-scale range (FSR) is divided (or resolved) into; where n is
equal to the number of bits.
RE LAT IVE ACCURACY (INL)
Relative accuracy, or integral nonlinearity, is the maximum de-
viation of the analog output (from the ideal) from a straight line
drawn between the end points. It is expressed in terms of least
significant bit (LSB), or as a percent of full scale.
DIFFE RE NT IAL NONLINE ARIT Y (DNL)
Differential nonlinearity is the worst case deviation of any adja-
cent analog output from the ideal 1 LSB step size. T he devia-
tion of the actual “step size” from the ideal step size of 1 LSB is
called the differential nonlinearity error or DNL. DACs with
DNL greater than
±
1 LSB may be nonmonotonic.
±
1/2 LSB
INL guarantees monotonicity and
±
1 LSB maximum DNL.
GAIN E RROR (G
FSE
)
Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of full-scale or in
terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.
Refer to PMI 1990/91 Data Book, Section 11, for additional
digital-to-analog converter definitions.
GE NE RAL CIRCUIT DE SCRIPT ION
CONVE RT E R SE CT ION
T he DAC8248 incorporates two multiplying 12-bit current out-
put CMOS digital-to-analog converters on one monolithic chip.
It contains two highly stable thin-film R-2R resistor ladder net-
works, two 12-bit DAC registers, two 8-bit input registers, and
two 4-bit input registers. It also contains the DAC control logic
circuitry and 24 single-pole, double-throw NMOS transistor
current switches.
Figure 1 shows a simplified circuit for the R-2R ladder and tran-
sistor switches for a single DAC. R is typically 11 k
. T he tran-
sistor switches are binarily scaled in size to maintain a constant
voltage drop across each switch. Figure 2 shows a single NMOS
transistor switch.
Figure 1. Simplified Single DAC Circuit Configuration.
(Switches Are Shown For All Digital Inputs at Zero)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC8248 | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| DAC8248AW | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| DAC8248EW | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| DAC8248FP | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| DAC8248FW | Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC8248GPZ | 功能描述:IC DAC 12BIT DUAL W/BUFF 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| DAC8248HP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DAC8248HS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 12-Bit 8-Bit Byte Double-Buffered CMOS D/A Converter |
| DAC8308 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| DAC8311 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.8V to 5.5V, 80mA, 14- and 16-Bit, Low-Power, Single-Channel,DIGITAL-TO-ANALOG CONVERTERS in SC70 Package |
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