參數(shù)資料
型號(hào)： DAC8222FPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/15頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT DUAL W/BUFF 24DIP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 15
設(shè)置時(shí)間： 1µs
位數(shù)： 12
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 24-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 24-PDIP
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 1M
DAC8222
–9–
REV. C
Table I. Mode Selection
Digital Inputs
Register Status
DAC A
DAC B
DAC
A/B
WR
LDAC
Input Register
DAC Register
Input Register
DAC Register
L
WRITE
LATCHED
WRITE
H
L
LATCHED
WRITE
L
H
WRITE
LATCHED
H
L
H
LATCHED
WRITE
LATCHED
X
H
L
LATCHED
WRITE
LATCHED
WRITE
X
H
LATCHED
L = Low, H = High, X = Don’t Care
WRITE TIMING CYCLES
Two timing diagrams are shown and are at the user’s discretion
which to use.
The TWO-CYCLE UPDATE, as the name implies, allows both
DAC registers to be loaded and the outputs updated in two
cycles. Data is first loaded into one DAC’s input register on the
first write cycle, and then new data loaded into the other DAC’s
input register while simultaneously updating both DAC outputs
on the second cycle.
The THREE-CYCLE UPDATE allows
DAC A and DAC B
registers to be loaded and analog output to be updated at a later
time. The first two cycles load both DACs as above, and the
third cycle updates the outputs.
The
LDAC and DAC A/DAC B control pins can be tied to-
gether and controlled with a single strobe. When using the DAC
in this configuration, DAC B must be loaded first.
INTERFACE CONTROL LOGIC
DAC A/DAC B (Pin 18)–DAC Selection. Active low for
DAC A and active high for DAC B.
WR (Pin 20)–WRITE. Active Low. Used to write data into
either DAC A or DAC B input registers, or active high latches
data into the input registers.
LDAC (Pin 19)–LOAD DAC. Active Low. Used to simulta-
neously transfer data from
DAC A and DAC B input registers
to both DAC outputs. The DAC becomes transparent (activity
on the digital inputs appear at the analog output) when both
WR and LDAC are low. Data is latched into the output regis-
ters on the rising edge of
LDAC.
Three-Cycle Update
Figure 23. Write Cycle Timing Diagram
Two-Cycle Update
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