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| 型號： | DAC8143FSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DAISY-CHAIN 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 設(shè)置時間： | 380ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 500µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.63M |
| 產(chǎn)品目錄頁面： | 786 (CN2011-ZH PDF) |
DAC8143
–7–
REV. C
ESD PROTECTION
The DAC8143 digital inputs have been designed with ESD
resistance incorporated through careful layout and the inclusion
of input protection circuitry.
Figure 11 shows the input protection diodes. High voltage static
charges applied to the digital inputs are shunted to the supply
and ground rails through forward biased diodes.
These protection diodes were designed to clamp the inputs well
below dangerous levels during static discharge conditions.
VDD
DTL/TTL/CMOS
INPUTS
Figure 11. Digital Input Protection
EQUIVALENT CIRCUIT ANALYSIS
Figures 12 and 13 show equivalent circuits for the DAC8143’s
internal DAC with all bits LOW and HIGH, respectively. The
reference current is switched to IOUT2 when all data bits are LOW,
and to IOUT1 when all bits are HIGH. The ILEAKAGE current
source is the combination of surface and junction leakages to the
substrate. The 1/4096 current source represents the constant
1-bit current drain through the ladder’s terminating resistor.
Output capacitance is dependent upon the digital input code.
This is because the capacitance of a MOS transistor changes
with applied gate voltage. This output capacitance varies be-
tween the low and high values.
RFEEDBACK
IOUT1
IOUT2
R = 10k
ILEAKAGE
60pF
ILEAKAGE
90pF
1/4096
R = 10k
IREF
VREF
Figure 12. Equivalent Circuit (All Inputs LOW)
IOUT2
ILEAKAGE
60pF
RFEEDBACK
IOUT1
R = 10k
ILEAKAGE
90pF
1/4096
R = 10k
IREF
VREF
Figure 13. Equivalent Circuit (All Inputs HIGH)
DYNAMIC PERFORMANCE
ANALOG OUTPUT IMPEDANCE
The output resistance, as in the case of the output capacitance,
varies with the digital input code. This resistance, looking back
into the IOUT1 terminal, varies between 11 k (the feedback
resistor alone when all digital input are LOW) and 7.5 k
(the
feedback resistor in parallel with approximately 30 k
of the
R-2R ladder network resistance when any single bit logic is
HIGH). Static accuracy and dynamic performance will be af-
fected by these variations.
The gain and phase stability of the output amplifier, board
layout, and power supply decoupling will all affect the dynamic
performance of the DAC8143. The use of a small compensation
capacitor may be required when high speed operational amplifi-
ers are used. It may be connected across the amplifier’s feed-
back resistor to provide the necessary phase compensation to
critically damp the output.
The considerations when using high speed amplifiers are:
1. Phase compensation (see Figures 16 and 17).
2. Power supply decoupling at the device socket and use of
proper grounding techniques.
OUTPUT AMPLIFIER CONSIDERATIONS
When using high speed op amps, a small feedback capacitor
(typically 5 pF–30 pF) should be used across the amplifiers to
minimize overshoot and ringing. For low speed or static
applications, ac specifications of the amplifier are not very criti-
cal. In high speed applications, slew rate, settling time, open-
loop gain and gain/phase margin specifications of the amplifier
should be selected for the desired performance. It has already
been noted that an offset can be caused by including the usual
bias current compensation resistor in the amplifier’s noninvert-
ing input terminal. This resistor should not be used. Instead, the
amplifier should have a bias current that is low over the tem-
perature range of interest.
Static accuracy is affected by the variation in the DAC’s output
resistance. This variation is best illustrated by using the circuit
of Figure 14 and the equation:
VERROR = VOS 1+
RFB
RO
VOS
VREF
RR
R
ETC
RFB
R2
OP-77
Figure 14. Simplified Circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DAC8143FSZ-REEL | 功能描述:IC DAC 12BIT DAISYCHAIN 16SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| DAC8162 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT |
| DAC8162SDGSR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14B,Dual,Lo Pwr Ultra-Lo Glitch DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC8162SDGST | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14B,Dual,Lo Pwr Ultra-Lo Glitch DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC8162SDSCR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14B,Dual,Lo Pwr Ultra-Lo Glitch DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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