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參數(shù)資料
| 型號： | DAC8143FS |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DAISY-CHAIN 16-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 47 |
| 設置時間： | 380ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 500µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.63M |
DAC8143
–10–
REV. C
In many applications, the DAC8143’s zero scale error and low
gain error, permit the elimination of external trimming compo-
nents without adverse effects on circuit performance.
For applications requiring a tighter gain error than 0.024% at
25
°C for the top grade part, or 0.048% for the lower grade part,
the circuit in Figure 17 may be used. Gain error may be trimmed
by adjusting R1.
The DAC register must first be loaded with all 1s. R1 is then
adjusted until VOUT = –VREF (4095/4096). In the case of an
adjustable VREF, R1 and RFEEDBACK may be omitted, with VREF
adjusted to yield the desired full-scale output.
BIPOLAR OPERATION (4-QUADRANT)
Figure 18 details a suggested circuit for bipolar, or offset binary,
operation. Table III shows the digital input-to-analog output
relationship. The circuit uses offset binary coding. Twos comple-
ment code can be converted to offset binary by software inver-
sion of the MSB or by the addition of an external inverter to the
MSB input.
Resistor R3, R4 and R5 must be selected to match within 0.01%
and must all be of the same (preferably metal foil) type to assure
temperature coefficient match. Mismatching between R3 and
R4 causes offset and full-scale error.
Calibration is performed by loading the DAC register with
1000 0000 0000 and adjusting R1 until VOUT = 0 V. R1 and
R2 may be omitted by adjusting the ratio of R3 to R4 to yield
VOUT = 0 V. Full scale can be adjusted by loading the DAC
register with 1111 1111 1111 and adjusting either the amplitude
of VREF or the value of R5 until the desired VOUT is achieved.
Table III. Bipolar (Offset Binary) Code Table
Digital Input
Nominal Analog Output
MSB
LSB
(VOUT as Shown in Figure 18)
1 1 1 1 1 1 1 1 1 1 1 1
+VREF
2047
2048
1 0 0 0 0 0 0 0 0 0 0 1
+VREF
1
2048
1 0 0 0 0 0 0 0 0 0 0 0
0
0 1 1 1 1 1 1 1 1 1 1 1
–VREF
1
2048
0 0 0 0 0 0 0 0 0 0 0 1
–VREF
2047
2048
0 0 0 0 0 0 0 0 0 0 0 0
–VREF
2048
NOTES
1Nominal full scale for the circuits of Figure 18 is given by
FS = VREF
2047
2048
.
2Nominal LSB magnitude for the circuits of Figure 18 is given by
LSB = VREF
1
2048
.
DAISY-CHAINING DAC8143s
Many applications use multiple serial input DACs that use
numerous interconnecting lines for address decoding and data
lines. In addition, they use some type of buffering to reduce
loading on the bus. The DAC8143 is ideal for just such an
application. It not only reduces the number of interconnecting
lines, but also reduces bus loading. The DAC8143 can be daisy-
chained with only three lines: one data line, one CLK line and
one load line, see Figure 19.
VOUT
1/2 OP200
+5V
R2
50
12
15
7
R1
100
SERIAL
DATA INPUT
VIN
14
15
1
2
3
6
13
4, 5
8-11
DGND
VREF
SRI
CONTROL
BITS
SRO
CONTROL
INPUTS
FROM
SYSTEM
RESET
BUFFERED SERIAL
DATA OUT
VDD
RFB
AGND
IOUT2
IOUT1
DAC8143
C1
10-33pF
COMMON GROUND
R3
10k
A1
R4
20k
R5
20k
1/2 OP200
A2
CLR
Figure 18. Bipolar Operation (4-Quadrant, Offset Binary)
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| DAC8143FSZ | 功能描述:IC DAC 12BIT DAISY-CHAIN 16-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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