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參數(shù)資料
| 型號(hào)： | DAC8143FS |
| 廠商： | PRECISION MONOLITHICS INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Serial Daisy-Chain CMOS D/A Converter |
| 中文描述： | 12-BIT DAC, PDSO16 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 181K |
| 代理商： | DAC8143FS |
DAC8143
–10–
REV. C
In many applications, the DAC8143’s zero scale error and low
gain error, permit the elimination of external trimming compo-
nents without adverse effects on circuit performance.
For applications requiring a tighter gain error than 0.024% at
25
°
C for the top grade part, or 0.048% for the lower grade part,
the circuit in Figure 17 may be used. Gain error may be trimmed
by adjusting R1.
The DAC register must first be loaded with all 1s. R1 is then
adjusted until V
OUT
= –V
REF
(4095/4096). In the case of an
adjustable V
REF
, R1 and R
FEEDBACK
may be omitted, with V
REF
adjusted to yield the desired full-scale output.
BIPOLAR OPERATION (4-QUADRANT)
Figure 18 details a suggested circuit for bipolar, or offset binary,
operation. Table III shows the digital input-to-analog output
relationship. The circuit uses offset binary coding. Twos comple-
ment code can be converted to offset binary by software inver-
sion of the MSB or by the addition of an external inverter to the
MSB input.
Resistor R3, R4 and R5 must be selected to match within 0.01%
and must all be of the same (preferably metal foil) type to assure
temperature coefficient match. Mismatching between R3 and
R4 causes offset and full-scale error.
Calibration is performed by loading the DAC register with
1000 0000 0000 and adjusting R1 until V
OUT
= 0 V. R1 and
R2 may be omitted by adjusting the ratio of R3 to R4 to yield
V
OUT
= 0 V. Full scale can be adjusted by loading the DAC
register with 1111 1111 1111 and adjusting either the amplitude
of V
REF
or the value of R5 until the desired V
OUT
is achieved.
Table III. Bipolar (Offset Binary) Code Table
Digital Input
MSB
Nominal Analog Output
(V
OUT
as Shown in Figure 18)
LSB
1 1 1 1 1 1 1 1 1 1 1 1
+
V
REF
2047
2048
1
2048
1 0 0 0 0 0 0 0 0 0 0 1
+
V
REF
1 0 0 0 0 0 0 0 0 0 0 0
0
0 1 1 1 1 1 1 1 1 1 1 1
–
V
REF
1
2048
2047
2048
2048
2048
0 0 0 0 0 0 0 0 0 0 0 1
–
V
REF
0 0 0 0 0 0 0 0 0 0 0 0
–
V
REF
NOTES
1
Nominal full scale for the circuits of Figure 18 is given by
2047
2048
FS
=
V
REF
.
2
Nominal LSB magnitude for the circuits of Figure 18 is given by
.
LSB
=
V
REF
1
2048
DAISY-CHAINING DAC8143s
Many applications use multiple serial input DACs that use
numerous interconnecting lines for address decoding and data
lines. In addition, they use some type of buffering to reduce
loading on the bus. The DAC8143 is ideal for just such an
application. It not only reduces the number of interconnecting
lines, but also reduces bus loading. The DAC8143 can be daisy-
chained with only three lines: one data line, one CLK line and
one load line, see Figure 19.
V
OUT
1/2 OP200
+5V
R2
50
V
12
15
7
R1
100
V
SERIAL
DATA INPUT
V
IN
14
15
1
2
3
6
13
4, 5
8-11
DGND
V
REF
CONTROL
BITS
SRI
SRO
CONTROL
INPUTS
FROM
SYSTEM
RESET
BUFFERED SERIAL
DATA OUT
V
DD
R
FB
AGND
I
OUT2
I
OUT1
DAC8143
C1
10-33pF
COMMON GROUND
R3
10k
V
A1
R4
20k
V
R5
20k
V
1/2 OP200
A2
CLR
Figure 18. Bipolar Operation (4-Quadrant, Offset Binary)
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