參數(shù)資料
型號(hào): DAC8043GP
廠商: Analog Devices Inc
文件頁數(shù): 5/16頁
文件大小: 0K
描述: IC DAC 12BIT MULTIPLY CMOS 8-DIP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 250ns
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 500µW
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 366k
DAC8043
Rev. E | Page 13 of 16
Bipolar Operation (4-Quadrant)
Figure 19 details a suggested circuit for bipolar, or offset binary,
operation. Table 7 shows the digital input to analog output
relationship. The circuit uses offset binary coding. Twos comple-
ment code can be converted to offset binary by software
inversion of the MSB or by the addition of an external inverter
to the MSB input.
Table 7. Bipolar (Offset Binary) Code Table1, 2
Digital Input
Nominal Analog Output
MSB
LSB
(VOUT as Shown in Figure 19)
1111 1111 1111
2048
2047
REF
V
1000 0000 0001
2048
1
REF
V
1000 0000 0000
0
0111 1111 1111
2048
1
REF
V
0000 0000 0001
2048
2047
REF
V
0000 0000 0000
2048
REF
V
1 Nominal full scale for Figure 19 circuits is given by
2048
2047
REF
V
FS
2 Nominal LSB magnitude for Figure 19 circuits is given by
2048
1
REF
V
LSB
Resistors R3, R4, and R5 must be selected to match within 0.01%,
and they all must be of the same (preferably metal foil) type to
ensure temperature coefficient matching. Mismatching between
R3 and R4 causes offset and full-scale errors, while an R5 to R4
and R3 mismatch results in full-scale error.
Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be
omitted, adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full
scale can be adjusted by loading the DAC register with 1111
1111 1111 and either adjusting the amplitude of VREF or the
value of R5 until the desired VOUT is achieved.
Analog/Digital Division
The transfer function for the DAC8043 connected in the
multiplying mode, as shown in Figure 16, Figure 17, and
12
3
2
1
2
...
2
12
3
2
1
IN
O
A
V
where AX assumes a value of 1 for an on bit and 0 for an off bit.
The transfer function is modified when the DAC is connected
in the feedback of an operational amplifier, as shown in Figure 18
and becomes
4
3
2
1
2
...
2
12
3
2
1
IN
O
A
V
The previous transfer function is the division of an analog
voltage (VREF) by a digital word. The amplifier goes to the rails
with all bits off because division by zero is infinity. With all bits
on the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB,
Bit 12, on.
DAC8043
RFB
VDD
5V
LD SRI CLK
VREF
IOUT
GND
DIGITAL
INPUT
VIN
00
271
-01
9
OP42
2
3
6
VOUT
Figure 18. Analog/Digital Divider
00
27
1-
0
18
VOUT
CONTROL
INPUTS
SERIAL
DATA
INPUT
ANALOG
COMMON
VIN
R2
50
R3
10k
5V
R4
20k
R5
20k
R1
100
C1
10.33pF
1/2
OP200
A2
DAC8043
RFB
VDD
VREF
IOUT
GND
CONTROL
BITS
SRI
1/2
OP200
A1
Figure 19. Bipolar Operation (4-Quadrant, Offset Binary)
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