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參數(shù)資料
| 型號： | DAC8043FS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Serial Input Multiplying CMOS D/A Converter |
| 中文描述： | SERIAL INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | SOL-16 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 189K |
| 代理商： | DAC8043FS |
DAC8043
–9–
REV. C
T able II. Bipolar (Offset Binary) Code T able
Digital Input
MSB
Nominal Analog Output
(V
OUT
as Shown in Figure 7)
LSB
1111 1111 1111
+V
REF
2047
2048
1000 0000 0001
+V
REF
1
2048
1000 0000 0000
0
0111 1111 1111
–V
REF
1
2048
0000 0000 0001
–V
REF
2047
2048
0000 0000 0000
–V
REF
2048
2048
NOT ES
1
Nominal full scale for the circuit of Figure 7 is given by
.
FS = V
REF
2047
2048
2
Nominal LSB magnitude for the circuit of Figure 7 is given by
.
LSB = V
REF
1
2048
Resistors R
3
, R
4
, and R
5
must be selected to match within 0.01%
and must all be of the same (preferably metal foil) type to assure
temperature coefficient matching. Mismatching between R
3
and
R
4
causes offset and full scale errors while an R
5
to R
4
and R
3
mismatch will result in full-scale error.
Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R
1
until V
OUT
= 0 V. R
1
and R
2
may
be omitted, adjusting the ratio of R
3
to R
4
to yield V
OUT
= 0 V.
Full scale can be adjusted by loading the DAC register with
1111 1111 1111 and either adjusting the amplitude of V
REF
or
the value of R
5
until the desired V
OUT
is achieved.
ANALOG/DIGIT AL DIVISION
T he transfer function for the DAC8043 connected in the multi-
plying mode as shown in Figures 5, 6 and 7 is:
V
O
= –V
IN
A
1
2
1
+
A
2
2
2
+
A
3
2
3
+
...
A
12
2
12
where A
X
assumes a value of 1 for an “ON” bit and 0 for an
“OFF” bit.
T he transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 8
and becomes:
V
O
=
±
V
IN
2
3
+
...
A
12
A
1
2
1
+
A
2
2
2
+
A
3
2
4
T he above transfer function is the division of an analog voltage
(V
REF
) by a digital word. T he amplifier goes to the rails with all
bits “OFF” since division by zero is infinity. With all bits “ON,”
the gain is 1 (
±
1 LSB). T he gain becomes 4096 with the LSB,
bit 12 “ON.”
Figure 7. Bipolar Operation (4-Quadrant, Offset Binary)
BIPOLAR OPE RAT ION (4-QUADRANT )
Figure 7 details a suggested circuit for bipolar, or offset binary
operation. T able II shows the digital input to analog output re-
lationship. T he circuit uses offset binary coding. T wo’s comple-
ment code can be converted to offset binary by software
inversion of the MSB or by the addition of an external inverter
to the MSB input.
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